A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.
Marc-Andre LaCroixHenry WongYun Hua LiuHuong HoSemyon LebedevPetar KrotnevDorin Alexandru NicolescuDmitry PetrovCarlos CarvalhoStephen AlieEuhan ChongFaisal Ahmed MusaDavide ToniettoPublished in: ISSCC (2019)
Keyphrases
- high speed
- power consumption
- ultra low power
- silicon on insulator
- low power
- signal to noise ratio
- cmos technology
- digital signal processing
- power dissipation
- signal processing
- low cost
- nm technology
- single chip
- real time
- power management
- sampling rate
- noise reduction
- power reduction
- chip design
- analog to digital converter