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Huong Ho
Publication Activity (10 Years)
Years Active: 2009-2021
Publications (10 Years): 2
Top Topics
Database Manager
Fpga Implementation
Fpga Technology
Modular Design
Top Venues
ISSCC
J. Signal Process. Syst.
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Publications
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Marc-Andre LaCroix
,
Euhan Chong
,
Weilun Shen
,
Ehud Nir
,
Faisal Ahmed Musa
,
Haitao Mei
,
Mohammad-Mahdi Mohsenpour
,
Semyon Lebedev
,
Babak Zamanlooy
,
Carlos Carvalho
,
Qian Xin
,
Dmitry Petrov
,
Henry Wong
,
Huong Ho
,
Yang Xu
,
Sina Naderi Shahi
,
Peter Krotnev
,
Chris Feist
,
Howard Huang
,
Davide Tonietto
8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2.
ISSCC
(2021)
Marc-Andre LaCroix
,
Henry Wong
,
Yun Hua Liu
,
Huong Ho
,
Semyon Lebedev
,
Petar Krotnev
,
Dorin Alexandru Nicolescu
,
Dmitry Petrov
,
Carlos Carvalho
,
Stephen Alie
,
Euhan Chong
,
Faisal Ahmed Musa
,
Davide Tonietto
A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss.
ISSCC
(2019)
Huong Ho
Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m).
J. Signal Process. Syst.
75 (3) (2014)
Huong Ho
,
Robert Klepko
,
Nam Ninh
,
Demin Wang
A high performance hardware architecture for multi-frame hierarchical motion estimation.
IEEE Trans. Consumer Electron.
57 (2) (2011)
Huong Ho
,
Valek Szwarc
,
Tad A. Kwasniewski
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination.
J. Signal Process. Syst.
61 (3) (2010)
Huong Ho
,
Valek Szwarc
,
Tad A. Kwasniewski
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications.
Int. J. Reconfigurable Comput.
2009 (2009)