Tad A. Kwasniewski

Publication Activity (10 Years)

Years Active: 1991-2017
Publications (10 Years): 1

Top Topics

Industrial Applications

Multiresolution

Top Venues

Publications

Leonard MacEachem, Xin-Jie Wang, Tad A. Kwasniewski
On-die power grid broadband model determination using a priori narrowband measurements. MWSCAS (2017)
Haizheng Guo, Tad A. Kwasniewski
A DLL-based fractional-N frequency synthesizer with a programmable injection clock. CCECE (2012)
Harry Tai, Peter Noel, Tad A. Kwasniewski
A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system. SoCC (2011)
Haizheng Guo, Bo Wang, Bangli Liang, Tad A. Kwasniewski, Robert Sobot
Optimized LNA for analog RF front-end circuit in brain-machine interface. WCNIS (2010)
Huong Ho, Valek Szwarc, Tad A. Kwasniewski
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. J. Signal Process. Syst. 61 (3) (2010)
Dianyong Chen, Bo Wang, Bangli Liang, Tad A. Kwasniewski
A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously. CCECE (2009)
Huong Ho, Valek Szwarc, Tad A. Kwasniewski
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications. Int. J. Reconfigurable Comput. 2009 (2009)
Bangli Liang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski, Zhigong Wang
A monolithic high modulation efficiency CMOS laser diode / modulator driver. ICT (2009)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. IEEE Trans. Very Large Scale Integr. Syst. 17 (12) (2009)
Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski
A full-rate truly monolithic CMOS CDR for low-cost applications. CCECE (2009)
Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tad A. Kwasniewski
A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. CCECE (2009)
Ramin Shariat-Yazdi, Tad A. Kwasniewski
Low complexity sphere decoding algorithms. ISWCS (2008)
Ramin Shariat-Yazdi, Tad A. Kwasniewski
A multi-mode sphere detector architecture for WLAN applications. SoCC (2008)
Bangli Liang, Tad A. Kwasniewski, Dianyong Chen
A 42-Gb/s Decision Circuit in 0.13µm CMOS. CNSR (2008)
Miao Li, Tad A. Kwasniewski, Shoujun Wang
A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops. ISCAS (2008)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. CICC (2007)
Muhammad Usama, Tad A. Kwasniewski
A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology. ISCAS (2007)
William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. DAC (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. CICC (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. SoCC (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction. IEEE Trans. Circuits Syst. II Express Briefs (11) (2006)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
An eye detection technique for clock and data recovery applications. ISCAS (2006)
Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang
A 0.18µm CMOS clock and data recovery circuit with extended operation range. ISCAS (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. CCECE (2006)
Miao Li, Tad A. Kwasniewski, Shoujun Wang
A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications. APCCAS (2006)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. Circuits, Signals, and Systems (2005)
Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski
A signal integrity-based link performance simulation platform. CICC (2005)
Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao
A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology. ASP-DAC (2005)
S. I. Ahmed, Tad A. Kwasniewski
An all-digital data recovery circuit optimization using Matlab/Simulink. ISCAS (5) (2005)
Charles E. Berndt, Tad A. Kwasniewski
A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane. IWSOC (2005)
Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications. IWSOC (2005)
Moeed Israr, Tad A. Kwasniewski
Turbo Codes - Digital IC Design. IWSOC (2005)
Jing Chen, Miao Li, Tad A. Kwasniewski
Decision feedback equalization for high-speed backplane data communications. ISCAS (2) (2005)
Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski
PLL-Based Fractional-N Frequency Synthesizers. IWSOC (2005)
Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang
A 0.18µm CMOS transceiver design for high-speed backplane data communications. ISCAS (2) (2005)
Arif A. Siddiqi, Tad A. Kwasniewski
2.4 GHz RF down-conversion mixers in standard CMOS technology. ISCAS (4) (2004)
Muhammad Usama, Tad A. Kwasniewski
Design and comparison of CMOS Current Mode Logic latches. ISCAS (4) (2004)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. CICC (2003)
Lizhong Sun, Tad A. Kwasniewski
A 1.25 GHz 0.35 /spl mu/m monolithic CMOS PLL clock generator for data communications. CICC (1999)
Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. ISCAS (2) (1999)
Lizhong Sun, Tad A. Kwasniewski, Kris Iniewski
A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops. ISCAS (2) (1999)
Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik
Is High Frequency Analog DFT Possible? VTS (1996)
D. P. Noel, Tad A. Kwasniewski, Samy A. Mahmoud, Wilf P. LeBlanc
A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems. VTC (1994)
Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski
A chip set for pipeline and parallel pipeline FFT architectures. J. VLSI Signal Process. 8 (3) (1994)
P. Mohanraj, David D. Falconer, Tad A. Kwasniewski
Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber Loops. IEEE J. Sel. Areas Commun. 9 (6) (1991)