Jingcheng Zhuang

Publication Activity (10 Years)

Years Active: 2003-2015
Publications (10 Years): 1

Top Topics

Prediction Accuracy

User Interface Design

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Inf. Media Technol.

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski
Design of Spur-Free ΣΔ Frequency Tuning Interface for Digitally Controlled Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (1) (2015)
Jingcheng Zhuang, Robert Bogdan Staszewski
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction. Inf. Media Technol. 9 (1) (2014)
Jingcheng Zhuang, Robert Bogdan Staszewski
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction. IPSJ Trans. Syst. LSI Des. Methodol. 7 (2014)
Jingcheng Zhuang, Robert Bogdan Staszewski
Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL. ECCTD (2013)
Jingcheng Zhuang, Robert Bogdan Staszewski
A low-power all-digital PLL architecture based on phase prediction. ICECS (2012)
Jingcheng Zhuang
Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers. IEEE Trans. Circuits Syst. II Express Briefs (8) (2011)
Jingcheng Zhuang, Bruce Andrew Doyle, Emerson S. Fang
Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End. IEEE Trans. Circuits Syst. II Express Briefs (5) (2011)
Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski
A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2010)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. IEEE Trans. Very Large Scale Integr. Syst. 17 (12) (2009)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. CICC (2007)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. CICC (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. SoCC (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction. IEEE Trans. Circuits Syst. II Express Briefs (11) (2006)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
An eye detection technique for clock and data recovery applications. ISCAS (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. CCECE (2006)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. Circuits, Signals, and Systems (2005)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. CICC (2003)