Qingjin Du

Publication Activity (10 Years)

Years Active: 2003-2009
Publications (10 Years): 0

Publications

Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. IEEE Trans. Very Large Scale Integr. Syst. 17 (12) (2009)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. CICC (2007)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. CICC (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. SoCC (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction. IEEE Trans. Circuits Syst. II Express Briefs (11) (2006)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
An eye detection technique for clock and data recovery applications. ISCAS (2006)
Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski
A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. CCECE (2006)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. Circuits, Signals, and Systems (2005)
Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski
A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. CICC (2003)