A low-power all-digital PLL architecture based on phase prediction.
Jingcheng ZhuangRobert Bogdan StaszewskiPublished in: ICECS (2012)
Keyphrases
- low power
- mixed signal
- vlsi architecture
- power consumption
- low cost
- vlsi circuits
- high speed
- cmos technology
- multi channel
- single chip
- high power
- cmos image sensor
- nm technology
- logic circuits
- low power consumption
- wireless transmission
- real time
- signal processor
- analog to digital converter
- gate array
- power saving
- general purpose
- delay insensitive
- power reduction
- low complexity