William Bereza

Publication Activity (10 Years)

Years Active: 2005-2009
Publications (10 Years): 0

Publications

Albert Vareljian, Mohsen Moussavi, William Bereza, Walter Fergusson, Charles E. Berndt, Rakesh H. Patel
Nonlinear behavior study in digital bang-bang PLL. CICC (2009)
Matt Fletcher, William Bereza, Mike Karlesky, Greg Williams
Evolving into Embedded Develop. AGILE (2007)
Walter Fergusson, Rakesh H. Patel, William Bereza
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. CICC (2007)
William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. DAC (2006)
Rakesh H. Patel, William Bereza
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. CICC (2006)
Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski
A signal integrity-based link performance simulation platform. CICC (2005)
Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. CICC (2005)