Tadeusz Kwasniewski

Publication Activity (10 Years)

Years Active: 1995-2016
Publications (10 Years): 4

Top Topics

Distorted Images

Reduced Reference

Subjective Quality

Top Venues

Int. J. Circuit Theory Appl.

Publications

Xinjie Wang, Tadeusz Kwasniewski
A reduced reference spur multiplying delay-locked loop. Int. J. Circuit Theory Appl. 44 (8) (2016)
Zhe Jiang, Haizheng Guo, Tadeusz Kwasniewski
Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design example. CCECE (2015)
Haizheng Guo, Tadeusz Kwasniewski
A DLL-based period synthesis. CCECE (2015)
Haizheng Guo, Tadeusz Kwasniewski
A DLL fractional M/N frequency synthesizer. CCECE (2015)
Haizheng Guo, Xinjie Wang, Tadeusz Kwasniewski
Spur analysis and reduction of edge combining DLL-based frequency multiplier. CCECE (2013)
Chao He, Tadeusz Kwasniewski
Bang-Bang CDR's acquisition, locking, and jitter tolerance. CCECE (2012)
Chao He, Tadeusz Kwasniewski
A novel fractional-N PLL architecture with hybrid of DCO and VCO. CCECE (2012)
Dianyong Chen, Bo Wang, Bangli Liang, Tadeusz Kwasniewski
A Simulator for High-Speed Backplane Transceivers. UKSim (2009)
Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tadeusz Kwasniewski
Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel. UKSim (2009)
Lei Zhang, Tadeusz Kwasniewski
FIR filter optimization using bit-edge equalization in high-speed backplane data transmission. Microelectron. J. 40 (10) (2009)
Tingjun Wen, Tadeusz Kwasniewski
Phase Noise Simulation and Modeling of ADPLL by SystemVerilog. BMAS (2008)
Dianyong Chen, Wei Wang, Tadeusz Kwasniewski
Design Considerations for a Direct RF Sampling Mixer. IEEE Trans. Circuits Syst. II Express Briefs (11) (2007)
Ramin Shariat-Yazdi, Tadeusz Kwasniewski
Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation. ICECS (2007)
S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski
Behavioral test benches for digital clock and data recovery circuits using Verilog-A. CICC (2005)
Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. CICC (2005)
Lizhong Sun, Tadeusz Kwasniewski
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator. IEEE J. Solid State Circuits 36 (6) (2001)
Manop Thamsirianunt, Tadeusz Kwasniewski
CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications. IEEE J. Solid State Circuits 32 (10) (1997)
Navid Foroudi, Tadeusz Kwasniewski
CMOS high-speed dual-modulus frequency divider for RF frequency synthesis. IEEE J. Solid State Circuits 30 (2) (1995)