A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator.
Lizhong SunTadeusz KwasniewskiPublished in: IEEE J. Solid State Circuits (2001)
Keyphrases
- high speed
- power consumption
- level set
- piecewise constant
- low cost
- framework for image segmentation
- power supply
- analog vlsi
- frequency band
- circuit design
- feedback loop
- low voltage
- low power
- differential equations
- level set method
- focal plane
- algebraic structure
- region competition
- delay insensitive
- vlsi circuits
- phase locked
- intel xeon
- image sensor
- neural network
- edge detection
- dual band
- cmos image sensor
- dielectric constant