Linda S. Milor

Publication Activity (10 Years)

Years Active: 1986-2016
Publications (10 Years): 9

Top Topics

Statistical Model

Room Temperature

Top Venues

Microelectron. Reliab.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Taizhi Liu, Chang-Chih Chen, Jiadong Wu, Linda S. Milor
SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection. ICCD (2016)
Fahad Ahmed, Linda S. Milor
Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Dae Hyun Kim, Linda S. Milor
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs. VTS (2016)
Soonyoung Cha, Dae Hyun Kim, Taizhi Liu, Linda S. Milor
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system. Microelectron. Reliab. 55 (9-10) (2015)
Dae Hyun Kim, Soonyoung Cha, Linda S. Milor
AVERT: An elaborate model for simulating variable retention time in DRAMs. Microelectron. Reliab. 55 (9-10) (2015)
Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda S. Milor
Processor-level reliability simulator for time-dependent gate dielectric breakdown. Microprocess. Microsystems 39 (8) (2015)
Chang-Chih Chen, Linda S. Milor
Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Taizhi Liu, Chang-Chih Chen, Linda S. Milor
Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines. ISQED (2015)
Dae Hyun Kim, Soonyoung Cha, Linda S. Milor
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs. Microelectron. Reliab. 55 (9-10) (2015)
Chang-Chih Chen, Muhammad Bashir, Linda S. Milor, Daehyun Kim, Sung Kyu Lim
Simulation of system backend dielectric reliability. Microelectron. J. 45 (10) (2014)
Soonyoung Cha, Chang-Chih Chen, Taizhi Liu, Linda S. Milor
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements. VTS (2014)
Zhengliang Lv, Linda S. Milor, Shiyuan Yang
Statistical model of NBTI and reliability simulation for analogue circuits. Microelectron. Reliab. 52 (9-10) (2012)
Muhammad Bashir, Linda S. Milor, Dae Hyun Kim, Sung Kyu Lim
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. Microelectron. Reliab. 50 (9-11) (2010)
Muhammad Bashir, Linda S. Milor
Towards a chip level reliability simulator for copper/low-k backend processes. DATE (2010)
Seyed-Abdollah Aftabjahani, Linda S. Milor
Timing Analysis with Compact Variation-Aware Standard Cell Models. CSIE (3) (2009)
Fahad Ahmed, Linda S. Milor
Reliable cache design with detection of gate oxide breakdown using BIST. ICCD (2009)
Seyed-Abdollah Aftabjahani, Linda S. Milor
Timing analysis with compact variation-aware standard cell models. Integr. 42 (3) (2009)
Muhammad Bashir, Linda S. Milor
A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation. Microelectron. Reliab. 49 (9-11) (2009)
Seyed-Abdollah Aftabjahani, Linda S. Milor
Fast Variation-Aware Statistical Dynamic Timing Analysis. CSIE (3) (2009)
Cheng Jia, Linda S. Milor
A BIST Circuit for DLL Fault Detection. IEEE Trans. Very Large Scale Integr. Syst. 16 (12) (2008)
Munkang Choi, Linda S. Milor
Diagnosis of Optical Lithography Faults With Product Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Seyed-Abdollah Aftabjahani, Linda S. Milor
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. ISQED (2008)
Munkang Choi, Linda S. Milor
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (7) (2006)
Changsoo Hong, Linda S. Milor, Munkang Choi, Tom Lin
Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models. Microelectron. Reliab. 45 (9-11) (2005)
Cheng Jia, Linda S. Milor
A BIST Solution for The Test of I/O Speed. ITC (2003)
Mien Li, Linda S. Milor
Computing Parametric Yield Adaptively Using Local Linear Models. DAC (1996)
Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik
Is High Frequency Analog DFT Possible? VTS (1996)
Linda S. Milor, Alberto L. Sangiovanni-Vincentelli
Minimizing production test time to detect faults in analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (6) (1994)
Linda S. Milor, V. Visvanathan
Detection of catastrophic faults in analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (2) (1989)
V. Visvanathan, Linda S. Milor
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. SCG (1986)