Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination.
Huong HoValek SzwarcTad A. KwasniewskiPublished in: J. Signal Process. Syst. (2010)
Keyphrases
- low complexity
- high speed
- systolic array
- digital signal
- signal processing
- digital signal processing
- motion estimation
- wireless video
- video encoding
- power reduction
- low cost
- computational complexity
- data flow
- bit plane
- hardware implementation
- vlsi architecture
- lower complexity
- video streaming
- multiple description coding
- distributed video coding
- video encoder
- high data rate
- low power