A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver.
James BaileyHossein ShakibaEhud NirGrigory MarderfeldPeter KrotnevMarc-Andre LaCroixDavid CassanDavide ToniettoPublished in: IEEE J. Solid State Circuits (2022)
Keyphrases
- low power
- high speed
- cmos technology
- decision feedback
- low cost
- power consumption
- nm technology
- power reduction
- low power consumption
- high power
- error propagation
- logic circuits
- single chip
- vlsi architecture
- digital signal processing
- wireless transmission
- wireless networks
- low voltage
- gate array
- power dissipation
- mixed signal
- vlsi circuits
- real time
- fading channels
- image sensor