Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS".
Shayan ShahramianAnthony Chan CarusonePublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- high speed
- cmos technology
- nm technology
- random access memory
- linear programming
- low power
- receding horizon
- analog to digital converter
- error correction
- dynamic programming
- markov chain
- decision feedback
- silicon on insulator
- real time
- low voltage
- power consumption
- objective function
- power supply
- linear program
- x ray
- optimal solution