Shoichiro Kawashima

Publication Activity (10 Years)

Years Active: 1998-2015
Publications (10 Years): 1

Top Topics

Rapid Development

Technological Advances

Top Venues

IEICE Trans. Electron.

Publications

Shoichiro Kawashima, Keizo Morita, Mitsuharu Nakazawa, Kazuaki Yamane, Mitsuhiro Ogai, Kuninori Kawabata, Kazuaki Takai, Yasuhiro Fujii, Ryoji Yasuda, Wensheng Wang, Yukinobu Hikosaka, Ken'ichi Inoue
An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology. IEICE Trans. Electron. (11) (2015)
Shoichiro Kawashima, Isao Fukushi, Keizo Morita, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Kazuaki Yamane, Tomohisa Hirayama, Toru Endo
A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip. IEICE Trans. Electron. (10) (2007)
Yadollah Eslami, Ali Sheikholeslami, Shoichi Masui, Toru Endo, Shoichiro Kawashima
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM). IEEE J. Solid State Circuits 39 (11) (2004)
Shoichi Masui, Tsuzumi Ninomiya, Michiya Oura, Wataru Yokozeki, Kenji Mukaida, Shoichiro Kawashima
A ferroelectric memory-based secure dynamically programmable gate array. IEEE J. Solid State Circuits 38 (5) (2003)
Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories. IEEE J. Solid State Circuits 38 (3) (2003)
Shoichiro Kawashima, Toru Endo, Akira Yamamoto, Ken-ichi Nakabayashi, Mitsuharu Nakazawa, Keizo Morita, Masaki Aoki
Bitline GND sensing technique for low-voltage operation FeRAM. IEEE J. Solid State Circuits 37 (5) (2002)
Joseph Wai Kit Siu, Yadollah Eslami, Ali Sheikholeslami, P. Glenn Gulak, Toru Endo, Shoichiro Kawashima
A 16 kb 1T1C FeRAM test chip using current-based reference scheme. CICC (2002)
Shoichiro Kawashima, Toshihiko Mori, Ryuhei Sasagawa, Makoto Hamaminato, Shigetoshi Wakayama, Kazuo Sukegawa, Isao Fukushi
A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's. IEEE J. Solid State Circuits 33 (5) (1998)