A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's.
Shoichiro KawashimaToshihiko MoriRyuhei SasagawaMakoto HamaminatoShigetoshi WakayamaKazuo SukegawaIsao FukushiPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- low power
- high speed
- high power
- power consumption
- vlsi architecture
- low cost
- cmos technology
- mixed signal
- single chip
- nm technology
- power management
- real time
- digital signal processing
- low power consumption
- vlsi circuits
- signal processor
- wireless transmission
- logic circuits
- gate array
- delay insensitive
- power reduction
- image sensor
- design methodology
- image processing