Toshihiko Mori

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 11

Top Topics

Metal Oxide Semiconductor

Error Correction

Magnetic Recording

Top Venues

GECCO (Companion)

Publications

Yohei Sobu, Yukito Tsunoda, Toshihiko Mori, Guoxiu Huang, Takuji Yamamoto, Shinsuke Tanaka, Takeshi Hoshida
High-speed and low-power optical DAC transmitter using all-silicon lumped segmented modulator directly driven by CMOS inverter driver. OFC (2024)
Yohei Sobu, Guoxiu Huang, Toshihiko Mori, Yukito Tsunoda, Takuji Yamamoto, Shinsuke Tanaka, Takeshi Hoshida
Highly power-efficient (2 pJ/bit), 128Gbps 16QAM signal generation of coherent optical DAC transmitter using 28-nm CMOS driver and all-silicon segmented modulator. OFC (2022)
Yukito Tsunoda, Takahiro Notsu, Yasufumi Sakai, Naoki Hamada, Toshihiko Mori, Teruo Ishihara, Atsuki Inoue
Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design. GECCO (Companion) (2019)
Tomoyuki Akiyama, Tsuyoshi Aoki, Takasi Simoyama, Akio Sugama, Shigeaki Sekiguchi, Yohei Sobu, Shinsuke Tanaka, Yu Tanaka, Seok-Hwan Jeong, Motoyuki Nishizawa, Nobuaki Hatori, Akinori Hayakawa, Toshihiko Mori
Error-Free Loopback of a Compact 25 Gb/s × 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error Correction. OFC (2018)
Tsuyoshi Aoki, Shigeaki Sekiguchi, Takasi Simoyama, Shinsuke Tanaka, Motoyuki Nishizawa, Nobuaki Hatori, Yohei Sobu, Akio Sugama, Tomoyuki Akiyama, Akinori Hayakawa, Hidenobu Muranaka, Toshihiko Mori, Y. Chen, Seok-Hwan Jeong, Yu Tanaka, Ken Morito
On-Package High-Density Silicon Photonics Optical Transceiver. ECOC (2018)
Tsuyoshi Aoki, Tomoyuki Akiyama, Akio Sugama, Akinori Hayakawa, Hidenobu Muranaka, Takasi Simoyama, Shinsuke Tanaka, Motoyuki Nishizawa, Nobuaki Hatori, Yohei Sobu, Yanfei Chen, Toshihiko Mori, Shigeaki Sekiguchi, Seok-Hwan Jeong, Yu Tanaka, Ken Morito
Low crosstalk simultaneous 12 ch × 25 Gb/s operation of high-density silicon photonics multichannel receiver. OFC (2017)
Shinsuke Tanaka, Takasi Simoyama, Tsuyoshi Aoki, Toshihiko Mori, Shigeaki Sekiguchi, Seok-Hwan Jeong, Tatsuya Usuki, Yu Tanaka, Ken Morito
Ultra-Low-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver. ECOC (2017)
Tsuyoshi Aoki, Shigeaki Sekiguchi, Takasi Simoyama, Shinsuke Tanaka, Motoyuki Nishizawa, Nobuaki Hatori, Yohei Sobu, Akio Sugama, Tomoyuki Akiyama, Akinori Hayakawa, Hidenobu Muranaka, Toshihiko Mori, Yanfei Chen, Seok-Hwan Jeong, Yu Tanaka, Ken Morito
Low Crosstalk Simultaneous 16-channel × 25 Gb/s Operation of High Density Silicon Photonics Optical Transceiver. ECOC (2017)
Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC (2016)
Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Jun Matsui, Takashi Shiraishi, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR. OFC (2016)
Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits (2016)
Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. ISSCC (2015)
Akinori Hayakawa, Masaya Kibune, Asako Toda, Shinsuke Tanaka, Takasi Simoyama, Yanfei Chen, Tomoyuki Akiyama, Shigekazu Okumura, Takeshi Baba, Tomoyuki Akahoshi, Seiji Ueno, Kazunori Maruyama, Masahiko Imai, Jian Hong Jiang, Pradip Thachile, Tamer Riad, Shigeaki Sekiguchi, Suguru Akiyama, Yu Tanaka, Ken Morito, Daisuke Mizutani, Toshihiko Mori, Takuji Yamamoto, Hiroji Ebe
A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects. OFC (2015)
Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. OFC (2015)
Takayuki Shibasaki, Yukito Tsunoda, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS. ISSCC (2015)
Yukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS. ISSCC (2015)
Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura
A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. VLSIC (2014)
Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori
3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. ISSCC (2014)
Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE. IEEE J. Solid State Circuits 49 (12) (2014)
Hiroyuki Nakamoto, Masahiro Kudo, Kimitoshi Niratsuka, Toshihiko Mori, Shinji Yamaura
A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications. ESSCIRC (2012)
Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura
A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. ISSCC (2012)
Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San, Tatsuji Matsuura, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori
SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Tomohiko Ogawa, Tatsuji Matsuura, Haruo Kobayashi, Nobukazu Takai, Masao Hotta, Hao San, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori
Non-binary SAR ADC with digital error correction for low power applications. APCCAS (2010)
Masato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing. ISSCC (2007)
Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura
A CMOS multichannel 10-Gb/s transceiver. IEEE J. Solid State Circuits 38 (12) (2003)
Masaki Yumoto, Kyungsuk Oh, Norihisa Komoda, Toshihiko Mori
Customization Rule Generation for Electronic Sales Promotion System in Wholesale Industry. WECWIS (1999)
Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, Shin Mitara
Low-power SRAM design using half-swing pulse-mode techniques. IEEE J. Solid State Circuits 33 (11) (1998)
Shoichiro Kawashima, Toshihiko Mori, Ryuhei Sasagawa, Makoto Hamaminato, Shigetoshi Wakayama, Kazuo Sukegawa, Isao Fukushi
A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's. IEEE J. Solid State Circuits 33 (5) (1998)