Non-binary SAR ADC with digital error correction for low power applications.
Tomohiko OgawaTatsuji MatsuuraHaruo KobayashiNobukazu TakaiMasao HottaHao SanAkira AbeKatsuyoshi YagiToshihiko MoriPublished in: APCCAS (2010)
Keyphrases
- error correction
- low power
- non binary
- mixed signal
- single chip
- power consumption
- analog to digital converter
- low cost
- high speed
- low density parity check
- ldpc codes
- wide dynamic range
- constraint satisfaction problems
- decoding algorithm
- error detection
- channel coding
- error correcting
- data hiding
- arc consistency
- cmos image sensor
- image sensor
- multi channel
- vlsi architecture
- frequent pattern mining
- cmos technology
- image reconstruction
- constraint satisfaction
- image quality