Tatsuji Matsuura

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 19

Top Topics

Constraint Satisfaction Problems

Binary Representation

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Eiki Kayama, Kenta Mori, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta
Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (5) (2023)
Taichi Maebou, Yuanchi Chen, Eiki Kayama, Kenta Mori, Hao San, Tatsuji Matsuura, Masao Hotta
A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS. ISPACS (2021)
Satoshi Sekine, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2021)
Eiki Kayama, Kenta Mori, Maebou Taichi, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta
A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. ISPACS (2021)
Kenta Mori, Eiki Kayama, Taichi Maebou, Yuanchi Chen, Hao San, Tatsuji Matsuura, Masao Hotta
A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier. ISPACS (2021)
Yuichiro Unno, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy. ISPACS (2019)
Yuki Tanaka, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
Duty Ratio and Capacitance Analysis of AC/DC Converter without Current Control Circuit. ISPACS (2019)
Yuichiro Kobayashi, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
Investigation of Hybrid ADC Combined with First-order Feedforward Incremental and SAR ADCs. ISPACS (2019)
Shuichiro Yamada, Toshiki Ohtsu, Minami Sasaki, Hao San, Tatsuji Matsuura, Masao Hotta
A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. ISPACS (2019)
Satoshi Sekine, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo
A Novel C-2αC Ladder Based Non-binary DAC for SAR-ADC Using Unit Capacitors. ISPACS (2018)
Kota Inoue, Tatsuji Matsuura, Akira Hyogo, Hao San
Non-binary cyclic and binary SAR hybrid ADC. MIXDES (2017)
Hiroyuki Tsuchiya, Yuki Watanabe, Koken Chin, Hao San, Tatsuji Matsuura, Masao Hotta
The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC. ISPACS (2017)
Hao San, Rompei Sugawara, Masao Hotta, Tatsuji Matsuura, Kazuyuki Aihara
A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2017)
Yuki Watanabe, Hayato Narita, Hiroyuki Tsuchiya, Tatsuji Matsuura, Hao San, Masao Hotta
A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. ASP-DAC (2017)
Hiroyuki Tsuchiya, Asato Uchiyama, Yuta Misima, Yuki Watanabe, Tatsuji Matsuura, Hao San, Masao Hotta
Non-binary cyclic ADC with correlated level shifting technique. ASP-DAC (2017)
Yuki Watanabe, Koken Chin, Hiroyuki Tsuchiya, Hao San, Tatsuji Matsuura, Masao Hotta
Experimental results of reconfigurable non-binary cyclic ADC. ISPACS (2017)
Tatsuji Matsuura
Integrated CMOS ADC - Tutorial review on recent hybrid SAR-ADCs. MIXDES (2017)
Koken Chin, Yuta Mishima, Yuki Watanabe, Hiroyuki Tsuchiya, Hao San, Tatsuji Matsuura, Masao Hotta
A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. ISPACS (2017)
Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo
A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2016)
Yuta Mishima, Toshiki Yamada, Asato Uchiyama, Tatsuji Matsuura, Hao San, Masao Hotta
A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion. ISPACS (2015)
Hao San, Rompei Sugawara, Masao Hotta, Tatsuji Matsuura, Kazuyuki Aihara
An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. CICC (2014)
Hideo Nakane, Ryuichi Ujiie, Takashi Oshima, Takaya Yamamoto, Keisuke Kimura, Yuichi Okuda, Kosuke Tsuiji, Tatsuji Matsuura
A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver. IEEE J. Solid State Circuits 49 (11) (2014)
Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Daiki Hirabayashi, Yuta Arakawa, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuji Yano, Tatsuhiro Gake, Takahiro J. Yamaguchi, Nobukazu Takai
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J. Electron. Test. 29 (6) (2013)
Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi, Yuta Doi, Osamu Kobayashi, Tatsuji Matsuura, Kiichi Niitsu, Yuta Arakawa, Daiki Hirabayashi, Yuji Yano, Tatsuhiro Gake, Nobukazu Takai, Takahiro J. Yamaguchi
Multi-bit sigma-delta TDC architecture with self-calibration. APCCAS (2012)
Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Satoshi Ito, Yohei Tan, Haruo Kobayashi
Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme. IEICE Trans. Electron. (7) (2011)
Tomohiko Ogawa, Haruo Kobayashi, Yohei Tan, Satoshi Ito, Satoshi Uemori, Nobukazu Takai, Kiichi Niitsu, Takahiro J. Yamaguchi, Tatsuji Matsuura, Nobuyoshi Ishikawa
SAR ADC that is configurable to optimize yield. APCCAS (2010)
Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San, Tatsuji Matsuura, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori
SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Tomohiko Ogawa, Tatsuji Matsuura, Haruo Kobayashi, Nobukazu Takai, Masao Hotta, Hao San, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori
Non-binary SAR ADC with digital error correction for low power applications. APCCAS (2010)
Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Yohei Tan, Satoshi Ito, Haruo Kobayashi
Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure. APCCAS (2010)
Tatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki
1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver. IEICE Trans. Electron. (6) (2009)
Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura
A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling. IEEE J. Solid State Circuits 43 (8) (2008)
Tatsuo Nakagawa, Tatsuji Matsuura, Eiki Imaizumi, Junya Kudoh, Goichi Ono, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura
1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver. ESSCIRC (2007)
Zhongyuan Chang, Tatsuji Matsuura
ΔΣ ADCs and Converter Techniques. ISSCC (2007)
Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. (6) (2007)
Takaya Yamamoto, Masumi Kasahara, Tatsuji Matsuura
A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling. CICC (2007)
Yasutoshi Aibara, Eiki Imaizumi, Hiroaki Takagishi, Tatsuji Matsuura
A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2006)
Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Masao Hotta, Tatsuji Matsuura
Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use. IEICE Trans. Electron. (6) (2006)
Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato
A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. IEEE J. Solid State Circuits 33 (11) (1998)
Koichi Ono, Tatsuji Matsuura, Eiki Imaizumi, Hisashi Okazawa, Ryuushi Shimokawa
Error suppressing encode logic of FCDL in a 6-b flash A/D converter. IEEE J. Solid State Circuits 32 (9) (1997)
Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta
Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits. IEEE J. Solid State Circuits 31 (5) (1996)
Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta
Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor. IEEE J. Solid State Circuits 31 (8) (1996)
Keiko Makie-Fukuda, Takafumi Kikuchi, Tatsuji Matsuura, Masao Hotta
Measurement of digital noise in mixed-signal integrated circuits. IEEE J. Solid State Circuits 30 (2) (1995)