Tetsuro Itakura

Publication Activity (10 Years)

Years Active: 1995-2022
Publications (10 Years): 10

Top Topics

Wide Dynamic Range

Power Consumption

Metal Oxide Semiconductor

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Toshiki Sugimoto, Tuan Thanh Ta, Koichi Kokubun, Satoshi Kondo, Tetsuro Itakura, Hisaaki Katagiri, Yutaka Ota, Mitsuhiro Sengoku, Honam Kwon, Keita Sasaki, Hiroshi Kubota, Kazuhiro Suzuki, Katsuyuki Kimura, Akihide Sai
1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation. VLSI Technology and Circuits (2022)
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27 (11) (2019)
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC (2017)
Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. ISSCC (2016)
Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. ISSCC (2016)
Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo
A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2016)
Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura
A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. ISCAS (2016)
Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura
20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting. A-SSCC (2016)
Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits 51 (12) (2016)
Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. ISSCC (2016)
Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura
A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. ISCAS (2015)
Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura
A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2015)
Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura
A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. ISCAS (2014)
Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. ISSCC (2014)
Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura
A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. VLSI-DAT (2013)
Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura
A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2013)
Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2013)
Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura
A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. ISSCC (2012)
Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. ISCAS (2012)
Masanori Furuta, Mai Nozawa, Tetsuro Itakura
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. IEEE J. Solid State Circuits 46 (6) (2011)
Takafumi Yamaji, Hiroshi Tanimoto, Junya Matsuno, Tetsuro Itakura
Harmonic Signal Rejection Schemes of Polyphase Downconverters. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2011)
Hiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki
A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller. ISSCC (2011)
Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. A-SSCC (2011)
Ippei Akita, Yuta Tsubouchi, Tetsuro Itakura, Michihiko Nishigaki, Hiroshi Uemura, Hideto Furuyama, Hideki Shibata
A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS. ESSCIRC (2011)
Ippei Akita, Tetsuro Itakura, Kei Shiraishi
Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch. IEEE Trans. Circuits Syst. II Express Briefs (11) (2011)
Akihide Sai, Takafumi Yamaji, Tetsuro Itakura
A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. ISSCC (2011)
Tetsuro Itakura
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Tomohiko Ito, Tetsuro Itakura
A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Masanori Furuta, Mai Nozawa, Tetsuro Itakura
8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. ISSCC (2010)
Rui Ito, Tetsuro Itakura
Phase Compensation Techniques for Low-Power Operational Amplifiers. IEICE Trans. Electron. (6) (2010)
Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. IEICE Trans. Electron. (6) (2008)
Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
An area-efficient sampling rate converter using negative feedback technique. ISCAS (2008)
Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2007)
Hidenori Okuni, Rui Ito, Hiroshi Yoshida, Tetsuro Itakura
A Direct Conversion Receiver with Fast-Settling DC Offset Canceller. PIMRC (2007)
Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme. IEEE J. Solid State Circuits 42 (11) (2007)
Osamu Watanabe, Rui Ito, Shigehito Saigusa, Tadashi Arai, Tetsuro Itakura
Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems. IEICE Trans. Electron. (6) (2007)
Shouhei Kousai, Mototsugu Hamada, Rui Ito, Tetsuro Itakura
A novel quality factor tuning scheme for active-RC filters. ESSCIRC (2007)
Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni
Balanced 3-phase analog signal processing for radio communications. ISCAS (2006)
Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. Solid State Circuits 41 (7) (2006)
Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2006)
Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. CICC (2006)
Rui Ito, Tetsuro Itakura, Tadashi Arai
Phase Compensation Technique for a Low-Power Transconductor. IEICE Trans. Electron. (6) (2005)
Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura
A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. IEICE Electron. Express 2 (15) (2005)
Hiroshi Yoshida, Takehiko Toyoda, Makoto Arai, Ryuichi Fujimoto, Toshiya Mitomo, Masato Ishii, Rui Ito, Tadashi Arai, Tetsuro Itakura, Hiroshi Tsurumi
A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA. IEICE Trans. Electron. (6) (2005)
Takeshi Ueno, Tetsuro Itakura
A 0.9 V 1.5 mW Continuous-Time Modulator for W-CDMA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2005)
Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. ESSCIRC (2005)
Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura
A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS. CICC (2005)
Tomohiko Ito, Takafumi Yamaji, Daisuke Kurose, Tetsuro Itakura
Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design. IEICE Electron. Express 1 (3) (2004)
Shoji Otaka, Mitsuyuki Ashida, Masato Ishii, Tetsuro Itakura
cancellation technique. IEEE J. Solid State Circuits 39 (12) (2004)
Toshiyuki Umeda, Shoji Otaka, Kenji Kojima, Tetsuro Itakura
A 1-V 2-GHz CMOS Up-Converter Using Self-Switching Mixers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2003)
Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda
A 402-output TFT-LCD driver IC with power control based on the number of colors selected. IEEE J. Solid State Circuits 38 (3) (2003)
Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi, Tetsuro Itakura
A four-input beam-forming downconverter for adaptive antennas. IEEE J. Solid State Circuits 38 (10) (2003)
Tetsuro Itakura, Hironori Minamizaki
A Two-Gain-Stage Amplifier without an On-Chip Miller Capacitor in an LCD Driver IC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2002)
Osamu Watanabe, Takafumi Yamaji, Tetsuro Itakura, Ichiro Hattori
A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. IEEE J. Solid State Circuits 37 (7) (2002)
Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura
A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range. IEEE J. Solid State Circuits 37 (5) (2002)
Tetsuro Itakura, Hironori Minamizaki, Tetsuya Saito, Tadashi Kuroda
A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors. CICC (2002)
Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Akira Yasuda, Ryuichi Fujimoto, Tadashi Arai, Hideyuki Kokatsu
A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. IEEE J. Solid State Circuits 34 (8) (1999)
Tetsuro Itakura, Takashi Ueno, Hiroshi Tanimoto, Tadashi Arai
A 2 V/sub pp/ linear input-range fully balanced CMOS transconductor and its application to a 2.5 V 2.5 MHz Gm-C LPF. CICC (1999)
Hiroshi Tanimoto, Tetsuro Itakura, Takashi Ueno, Akira Yasuda, Kazuhiro Oda
An offset-free LPF for π/4-shift QPSK signal generator. IEEE J. Solid State Circuits 31 (12) (1996)
Tetsuro Itakura, Tetsuya Iida
A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier. IEEE J. Solid State Circuits 31 (6) (1996)
Takeshi Shima, Tetsuro Itakura, Shigeru Yamada, Hironori Minamizaki, Takeshi Ishioka
Principle and applications of an autocharge-compensated sample and hold circuit. IEEE J. Solid State Circuits 30 (8) (1995)