28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.
Kentaro YoshiokaTomohiko SugimotoNaoya WakiSinnyoung KimDaisuke KuroseHirotomo IshiiMasanori FurutaAkihide SaiTetsuro ItakuraPublished in: ISSCC (2017)