Masanori Furuta

Publication Activity (10 Years)

Years Active: 2003-2022
Publications (10 Years): 14

Top Topics

Noise Cancellation

Metal Oxide Semiconductor

Cmos Image Sensor

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Zhaoqi Chen, Alia Nasrallah, Milad Alemohammad, Masanori Furuta, Ralph Etienne-Cummings
Neuromorphic model of hippocampus place cells using an oscillatory interference technique for hardware implementation. Neuromorph. Comput. Eng. 2 (4) (2022)
Masanori Furuta, Koichiro Ban, Daisuke Kobayashi, Tomoyuki Shibata
An Efficient Implementation of FPGA-based Object Detection Using Multi-scale Attention. MWSCAS (2021)
Alia Nasrallah, Zhaoqi Chen, Milad Alemohammad, Adyant Balaji, Adam B. Cellon, Masanori Furuta, Ralph Etienne-Cummings
Velocity-Tuned Oscillators for NeuroSLAM and Spatial Navigation. ISCAS (2020)
Adam B. Cellon, Adebayo A. Eisape, Masanori Furuta, Ralph Etienne-Cummings
Velocity-Controlled Oscillators for Hippocampal Navigation on Spiking Neuromorphic Hardware. ISCAS (2019)
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27 (11) (2019)
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC (2017)
Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. ISSCC (2016)
Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. ISSCC (2016)
Junya Matsuno, Masanori Furuta, Tetsuro Itakura, Tatsuji Matsuura, Akira Hyogo
A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2016)
Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura
A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. ISCAS (2016)
Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits 51 (12) (2016)
Kei Shiraishi, Yasuhiro Shinozuka, Tomonori Yamashita, Kazuhide Sugiura, Naoto Watanabe, Ryuta Okamoto, Tatsuji Ashitani, Masanori Furuta, Tetsuro Itakura
6.7 A 1.2e- temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA. ISSCC (2016)
Yasuhiro Shinozuka, Kei Shiraishi, Masanori Furuta, Tetsuro Itakura
A single-slope based low-noise ADC with input-signal-dependent multiple sampling scheme for CMOS image sensors. ISCAS (2015)
Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura
A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2015)
Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura
A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. ISCAS (2014)
Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. ISSCC (2014)
Junya Matsuno, Masahiro Hosoya, Masanori Furuta, Tetsuro Itakura
A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier. VLSI-DAT (2013)
Masanori Furuta, Ippei Akita, Junya Matsuno, Tetsuro Itakura
A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2013)
Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2013)
Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura
All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. ISCAS (2012)
Masanori Furuta, Mai Nozawa, Tetsuro Itakura
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique. IEEE J. Solid State Circuits 46 (6) (2011)
Ippei Akita, Masanori Furuta, Junya Matsuno, Tetsuro Itakura
A 7-bit 1.5-GS/s time-interleaved SAR ADC with dynamic track-and-hold amplifier. A-SSCC (2011)
Masanori Furuta, Mai Nozawa, Tetsuro Itakura
8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. ISSCC (2010)
Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura
An area-efficient sampling rate converter using negative feedback technique. ISCAS (2008)
Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura
Design of Parallel Image Compression Circuits for High-speed CMOS Image Sensors. Inf. Media Technol. 2 (3) (2007)
Jong-Ho Park, Shoji Kawahito, Masanori Furuta, Masaaki Sasaki, Yasuo Wakamori, Mitsuhito Mase, Yukihiro Ohta
A Wide Dynamic Range CMOS Image Sensor with Improved 12-bit Column Parallel Cyclic ADCs. Inf. Media Technol. 2 (3) (2007)
Kazutaka Honda, Masanori Furuta, Shoji Kawahito
A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques. IEEE J. Solid State Circuits 42 (4) (2007)
Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji Kawahito
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters. IEEE J. Solid State Circuits 42 (4) (2007)
Masanori Furuta, Shoji Kawahito, Daisuke Miyazaki
A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters. IEEE Trans. Instrum. Meas. 56 (6) (2007)
Yukinari Nishikawa, Shoji Kawahito, Masanori Furuta, Toshihiro Tamura
A High-Speed CMOS Image Sensor with On-chip Parallel Image Compression Circuits. CICC (2007)
Zheng Liu, Masanori Furuta, Shoji Kawahito
Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits. IEICE Trans. Electron. (6) (2006)
Kazutaka Honda, Masanori Furuta, Shoji Kawahito
A 1V 10b 125MSample/s A/D Converter Using Cascade Amp-Sharing and Capacitance Coupling Techniues. ISCAS (2006)
Mitsuhito Mase, Shoji Kawahito, Masaaki Sasaki, Yasuo Wakamori, Masanori Furuta
A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters. IEEE J. Solid State Circuits 40 (12) (2005)
Masanori Furuta, Shoji Kawahito, Toru Inoue, Yukinari Nishikawa
A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors. ESSCIRC (2005)
Shoji Kawahito, Kazutaka Honda, Masanori Furuta, Nobuhiro Kawai, Daisuke Miyazaki
Low-Power Design of High-Speed A/D Converters. IEICE Trans. Electron. (4) (2005)
Atsushi Suzuki, Shoji Kawahito, Daisuke Miyazaki, Masanori Furuta
A digitally skew correctable multi-phase clock generator using a master-slave DLL. ISCAS (1) (2003)
Daisuke Miyazaki, Masanori Furuta, Shoji Kawahito
A 75mW 10bit 120MSample/s parallel pipeline ADC. ESSCIRC (2003)
Daisuke Miyazaki, Shoji Kawahito, Masanori Furuta
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture. IEEE J. Solid State Circuits 38 (2) (2003)