A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.
Akihide SaiHidenori OkuniTuan Thanh TaSatoshi KondoTakashi TokairinMasanori FurutaTetsuro ItakuraPublished in: IEEE J. Solid State Circuits (2016)