Takashi Tokairin

Publication Activity (10 Years)

Years Active: 2006-2018
Publications (10 Years): 6

Top Topics

Fully Integrated

Protein Folding

Top Venues

Publications

Tuan Thanh Ta, Yosuke Ogasawara, Tong Wang, Masayoshi Oshiro, Naotaka Koide, Akihide Sai, Takashi Tokairin
A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX. ESSCIRC (2018)
Tong Wang, Yosuke Ogasawara, Yuki Tuda, Tuan Thanh Ta, Masayoshi Oshiro, Jun Ihara, Tatsuhiko Maruyama, Toru Hashimoto, Akihide Sai, Takashi Tokairin
An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX. VLSI Circuits (2018)
Masayoshi Oshiro, Tatsuhiko Maruyama, Takashi Tokairin, Yuki Tuda, Tong Wang, Naotaka Koide, Yosuke Ogasawara, Tuan Thanh Ta, Hiroshi Yoshida, Kenichi Sami
A 3.2mA-RX 3.5mA-TX Fully Integrated SoC for Bluetooth Low Energy System. IEICE Trans. Electron. (10) (2017)
Masayoshi Oshiro, Tatsuhiko Maruyama, Takashi Tokairin, Yuki Tuda, Tong Wang, Naotaka Koide, Yosuke Ogasawara, Tuan Thanh Ta, Hiroshi Yoshida, Kenichi Sami
A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy. A-SSCC (2016)
Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. ISSCC (2016)
Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. IEEE J. Solid State Circuits 51 (12) (2016)
Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. VLSIC (2012)
Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi
A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme. IEEE J. Solid State Circuits 46 (3) (2011)
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. IEEE J. Solid State Circuits 45 (12) (2010)
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. ISSCC (2010)
Tadashi Maeda, Takashi Tokairin
Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Tadashi Maeda, Hitoshi Yano, Shinichi Hori, Noriaki Matsuno, Tomoyuki Yamase, Takashi Tokairin, Robert Walkington, Nobuhide Yoshida, Keiichi Numata, Kiyoshi Yanagisawa, Yuji Takahashi, Masahiro Fujii, Hikaru Hida
Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz. IEEE J. Solid State Circuits 41 (2) (2006)
Tadashi Maeda, Noriaki Matsuno, Shinichi Hori, Tomoyuki Yamase, Takashi Tokairin, Kiyoshi Yanagisawa, Hitoshi Yano, Robert Walkington, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Hikaru Hida
A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver. IEEE J. Solid State Circuits 41 (11) (2006)