Muneo Fukaishi

Publication Activity (10 Years)

Years Active: 1996-2012
Publications (10 Years): 0

Top Venues

IEEE J. Solid State Circuits

Publications

Masaki Kitsunezuka, Hiroshi Kodama, Naoki Oshima, Kazuaki Kunihiro, Tadashi Maeda, Muneo Fukaishi
A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems. IEEE J. Solid State Circuits 47 (5) (2012)
Shingo Takahashi, Nobuhide Yoshida, Kenichi Maruhashi, Muneo Fukaishi
Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems. ISSCC (2011)
Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi
A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme. IEEE J. Solid State Circuits 46 (3) (2011)
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. IEEE J. Solid State Circuits 45 (12) (2010)
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. ISSCC (2010)
Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau, Nicolas Deparis, Nathalie Rolland, Muneo Fukaishi, Pierre Vincent
A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI. IEEE J. Solid State Circuits 45 (7) (2010)
Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau, Nicolas Deparis, Nathalie Rolland, Muneo Fukaishi, Pierre Vincent
A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI. ESSCIRC (2009)
Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits 42 (1) (2007)
Robert Payne, Muneo Fukaishi
Multi-GB/s Transceivers. ISSCC (2007)
Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC (2006)
Kouichi Yamaguchi, Muneo Fukaishi
Channel-Count-Independent BIST for Multi-Channel SerDes. IEICE Trans. Electron. (3) (2006)
Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. ISSCC (2006)
Yoshiharu Kudoh, Muneo Fukaishi, Masayuki Mizuno
A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer. IEEE J. Solid State Circuits 38 (5) (2003)
Kouichi Yamaguchi, Muneo Fukaishi, Takehiko Sakamoto, Naoto Akiyama, Kazuyuki Nakamura
A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture. IEEE J. Solid State Circuits 36 (11) (2001)
Takashi Yoshikawa, Ichiro Hatakeyama, Kazunori Miyoshi, Kazuhiko Kurata, Juni-Ichi Sasaki, Nobuharu Kami, Takara Sugimoto, Muneo Fukaishi, Kazuyuki Nakamura, Kei Tanaka, Hiroaki Nishi, Tomohiro Kudoh
Optical interconnection as an IP macro of a CMOS library. Hot Interconnects (2001)
Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC (2001)
Muneo Fukaishi, Kazuyuki Nakamura, Hideki Heiuchi, Yoshinori Hirota, Yoetsu Nakazawa, Hidenori Ikeno, Hiroshi Hayama, Michio Yotsuyanagi
A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays. IEEE J. Solid State Circuits 35 (11) (2000)
Muneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuyanagi
A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications. IEEE J. Solid State Circuits 34 (9) (1999)
Muneo Fukaishi, Kazuyuki Nakamura, Masaharu Sato, Yutaka Tsutsui, Syuji Kishi, Michio Yotsuyanagi
A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture. IEEE J. Solid State Circuits 33 (12) (1998)
Masahiro Fujii, Keiichi Numata, Tadashi Maeda, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa
A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's. IEEE Trans. Very Large Scale Integr. Syst. 6 (1) (1998)
Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikam Hida, Yasuo Ohno
A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's. IEEE J. Solid State Circuits 31 (2) (1996)
Tadashi Maeda, Keiichi Numata, Masahiro Fujii, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa
An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF). IEEE J. Solid State Circuits 31 (9) (1996)