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A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO.

Koichiro MinamiMuneo FukaishiMasayuki MizunoHideaki OnishiKenji NodaKiyotaka ImaiTadahiko HoriuchiHiroshi YamaguchiTakanori SatoKazuyuki NakamuraMasakazu Yaniashina
Published in: CICC (2001)
Keyphrases
  • phase locked loop
  • high speed
  • power consumption
  • low power
  • analog vlsi
  • frequency band
  • low cost
  • multipath
  • circuit design
  • power supply
  • delay insensitive
  • image sensor
  • cmos technology