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Kiyotaka Imai
Publication Activity (10 Years)
Years Active: 1995-2005
Publications (10 Years): 0
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Publications
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Kiyotaka Imai
,
Yasushi Yamagata
,
Sadaaki Masuoka
,
Naohiko Kimuzuka
,
Yuri Yasuda
,
Mitsuhiro Togo
,
Masahiro Ikeda
,
Yasutaka Nakashiba
Device technology for body biasing scheme.
ISCAS (1)
(2005)
Koichiro Minami
,
Muneo Fukaishi
,
Masayuki Mizuno
,
Hideaki Onishi
,
Kenji Noda
,
Kiyotaka Imai
,
Tadahiko Horiuchi
,
Hiroshi Yamaguchi
,
Takanori Sato
,
Kazuyuki Nakamura
,
Masakazu Yaniashina
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO.
CICC
(2001)
Yuhua Cheng
,
Kai Chen
,
Kiyotaka Imai
,
Chenming Hu
A unified MOSFET channel charge model for device modeling in circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
17 (8) (1998)
Hitoshi Okamura
,
Takao Atsumo
,
Koichi Takeda
,
Masahide Takada
,
Kiyotaka Imai
,
Yasushi Kinoshita
,
Tom Yamazaki
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump.
IEEE J. Solid State Circuits
31 (1) (1996)
Hitoshi Okamura
,
Hideo Toyoshima
,
Koichi Takeda
,
Takashi Oguri
,
Satoshi Nakamura
,
Masahide Takada
,
Kiyotaka Imai
,
Yasushi Kinoshita
,
Hiroshi Yoshida
,
Tom Yamazaki
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors.
IEEE J. Solid State Circuits
30 (11) (1995)