Chenming Hu

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 22

Top Topics

Electrical Properties

Computational Fluid Dynamics

Design Space Exploration

Top Venues

Comput. Electron. Agric.

Publications

Chenming Hu, Zheng Fang, Kuanxu Hou, Delei Kong, Junjie Jiang, Hao Zhuang, Mingyuan Sun, Xinjie Huang
Spike-EVPR: Deep Spiking Residual Network with Cross-Representation Aggregation for Event-Based Visual Place Recognition. CoRR (2024)
Hao Zhuang, Zheng Fang, Xinjie Huang, Kuanxu Hou, Delei Kong, Chenming Hu
EV-MGRFlowNet: Motion-Guided Recurrent Network for Unsupervised Event-Based Optical Flow With Hybrid Motion-Compensation Loss. IEEE Trans. Instrum. Meas. 73 (2024)
Shuping Fang, Yu Ru, Chenming Hu, Fengbo Yang, Jiangkun Xue, Jie Zhou
Planning the temporary takeoff/landing site's location for a pesticide spraying helicopter based on an intelligent fusion algorithm. Comput. Electron. Agric. 209 (2023)
Hao Zhuang, Xinjie Huang, Kuanxu Hou, Delei Kong, Chenming Hu, Zheng Fang
EV-MGRFlowNet: Motion-Guided Recurrent Network for Unsupervised Event-based Optical Flow with Hybrid Motion-Compensation Loss. CoRR (2023)
Girish Pahwa, Ayushi Sharma, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu
Robust Compact Model of High-Voltage MOSFET's Drift Region. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Li-Chen Wang, W. Li, Nirmaan Shanker, Suraj S. Cheema, Shang-Lin Hsu, S. Volkman, U. Sikder, C. Garg, J.-H. Park, Y.-H. Liao, Y.-K. Lin, Chenming Hu, Sayeef S. Salahuddin
Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack. VLSI Technology and Circuits (2023)
Nirmaan Shanker, Li-Chen Wang, Suraj Cheema, Wenshen Li, Nilotpal Choudhury, Chenming Hu, Souvik Mahapatra, Sayeef S. Salahuddin
On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs. VLSI Technology and Circuits (2022)
Chetan K. Dabhi, Girish Pahwa, Sayeef S. Salahuddin, Chenming Hu
Compact Model for Trap Assisted Tunneling based GIDL. DRC (2022)
Surila Guglani, Avirup Dasgupta, Ming-Yen Kao, Chenming Hu, Sourajeet Roy
Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs. DRC (2022)
Zhiyong Li, Chenming Hu, Ke Nai, Jin Yuan
Siamese target estimation network with AIoU loss for real-time visual tracking. J. Vis. Commun. Image Represent. 77 (2021)
Darsen D. Lu, Mohan V. Dunga, Ali M. Niknejad, Chenming Hu, Fu-Xiang Liang, Wei-Chen Hung, Jia-Wei Lee, Chun-Hsiang Hsu, Meng-Hsueh Chiang
Compact Device Models for FinFET and Beyond. CoRR (2020)
Ava J. Tan, Li-Chen Wang, Yu-Hung Liao, Jong-Ho Bae, Chenming Hu, Sayeef S. Salahuddin
Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET. DRC (2020)
Haidong Wang, Saizhou Wang, Jingyi Lv, Chenming Hu, Zhiyong Li
Non-local attention association scheme for online multi-object tracking. Image Vis. Comput. 102 (2020)
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin
A Density Metric for Semiconductor Technology [Point of View]. Proc. IEEE 108 (4) (2020)
H.-S. Philip Wong, Kerem Akarvardar, Dimitri A. Antoniadis, Jeffrey Bokor, Chenming Hu, Tsu-Jae King Liu, Subhasish Mitra, James D. Plummer, Sayeef S. Salahuddin, Lei Deng, Xin-Guo Li, Song Han, Luping Shi, Yuan Xie, Elias Yaacoub, Mohamed-Slim Alouini, Ahmed Douik, Hayssam Dahrouj, Tareq Y. Al-Naffouri
Scanning the Issue. Proc. IEEE 108 (4) (2020)
Longhuan Du, Chenming Hu, Chaowu Yang, Li Yang, Huarui Du, Qingyun Li, Chunlin Yu, Lingzhi Xie, Xiaosong Jiang
Investigation of a preliminary ventilation energy-recovery system for poultry houses. Comput. Electron. Agric. 175 (2020)
Longhuan Du, Li Yang, Chaowu Yang, Robert Dominy, Chenming Hu, Huarui Du, Qingyun Li, Chunlin Yu, Lingzhi Xie, Xiaosong Jiang
Investigation of bio-aerosol dispersion in a tunnel-ventilated poultry house. Comput. Electron. Agric. 167 (2019)
Longhuan Du, Chaowu Yang, Robert Dominy, Li Yang, Chenming Hu, Huarui Du, Qingyun Li, Chunlin Yu, Lingzhi Xie, Xiaosong Jiang
Computational Fluid Dynamics aided investigation and optimization of a tunnel-ventilated poultry house in China. Comput. Electron. Agric. 159 (2019)
Chetan Gupta, Ravi Goel, Harshit Agarwal, Chenming Hu, Yogesh Singh Chauhan
BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design. CICC (2019)
Sandeep Kumar Samal, Sourabh Khandelwal, Asif I. Khan, Sayeef S. Salahuddin, Chenming Hu, Sung Kyu Lim
Full chip power benefits with negative capacitance FETs. ISLPED (2017)
Avirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Ethirajan Tamilmani, Chenming Hu, Yogesh Singh Chauhan
Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs. VLSI Design (2017)
Pragya Kushwaha, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan
Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG. Microelectron. J. 56 (2016)
Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (8) (2015)
Juan Pablo Duarte, Sourabh Khandelwal, Aditya Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan
BSIM-CMG: Standard FinFET compact model for advanced circuit design. ESSCIRC (2015)
Navid Paydavosi, Sriramkumar Venugopalan, Yogesh Singh Chauhan, Juan Pablo Duarte, Srivatsava Jandhyala, Ali M. Niknejad, Chenming Hu
BSIM - SPICE Models Enable FinFET and UTB IC Designs. IEEE Access 1 (2013)
Navid Paydavosi, Sriramkumar Venugopalan, Angada B. Sachid, Ali M. Niknejad, Chenming Hu, Sagnik Dey, Samuel Martin, Xin Zhang
Flicker noise in advanced CMOS technology: Effects of halo implant. ESSDERC (2013)
Sriramkumar Venugopalan, Krishnanshu Dandu, Samuel Martin, Richard Taylor, Claude Cirba, Xin Zhang, Ali M. Niknejad, Chenming Hu
A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6. CICC (2012)
Maria-Anna Chalkiadaki, Anurag Mangla, Christian C. Enz, Yogesh Singh Chauhan, Mohammed Ahosan Ul Karim, Sriramkumar Venugopalan, Ali M. Niknejad, Chenming Hu
Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology. ESSCIRC (2012)
Yogesh Singh Chauhan, Sriramkumar Venugopalan, Mohammed A. Karim, Sourabh Khandelwal, Navid Paydavosi, Pankaj Thakur, Ali M. Niknejad, Chenming Hu
BSIM - Industry standard compact MOSFET models. ESSCIRC (2012)
Chenming Hu
New sub-20nm transistors: why and how. DAC (2011)
Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu
Compact Modeling of Variation in FinFET SRAM Cells. IEEE Des. Test Comput. 27 (2) (2010)
Jin He, Jane Xi, Mansun Chan, Hui Wan, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu
Charge-Based Core and the Model Architecture of BSIM5. ISQED (2005)
Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. IEEE Trans. Very Large Scale Integr. Syst. 13 (1) (2005)
Xuemei Xi, Jin He, Mohan V. Dunga, Chung-Hsun Lin, Babak Heydari, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu
The next generation BSIM for sub-100nm mixed-signal circuit simulation. CICC (2004)
Jin He, Xuemei Xi, Mansun Chan, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu
A Non-Charge-Sheet Based Analytical Model of Undoped Symmetric Double-Gate MOSFETs Using SPP Approach. ISQED (2004)
Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester
Improved a priori interconnect predictions and technology extrapolation in the GTX system. IEEE Trans. Very Large Scale Integr. Syst. 11 (1) (2003)
Ke-Wei Su, Yi-Ming Sheu, Chung-Kai Lin, Sheng-Jier Yang, Wen-Jya Liang, Xuemei Xi, Chung-Shi Chiang, Jaw-Kang Her, Yu-Tai Chia, Carlos H. Diaz, Chenming Hu
A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics. CICC (2003)
Leland Chang, Yang-Kyu Choi, Daewon Ha, Pushkar Ranade, Shiying Xiong, Jeffrey Bokor, Chenming Hu, Tsu-Jae King
Extremely scaled silicon nano-CMOS devices. Proc. IEEE 91 (11) (2003)
Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Yu Cao, Robert A. Groves, Xuejue Huang, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King, Chenming Hu
Frequency-independent equivalent-circuit model for on-chip spiral inductors. IEEE J. Solid State Circuits 38 (3) (2003)
Xuejue Huang, Phillip J. Restle, Thomas J. Bucelot, Yu Cao, Tsu-Jae King, Chenming Hu
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. IEEE J. Solid State Circuits 38 (3) (2003)
Pin Su, Samel K. H. Fung, Peter W. Wyatt, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. CICC (2003)
Mansun Chan, Xuemei Xi, Jin He, Kanyu M. Cao, Mohan V. Dunga, Ali M. Niknejad, Ping K. Ko, Chenming Hu
Practical compact modeling approaches and options for sub-0.1 mum CMOS technologies. Microelectron. Reliab. 43 (3) (2003)
Yu Cao, Robert A. Groves, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Xuejue Huang, Tsu-Jae King, Chenming Hu
Frequency-independent equivalent circuit model for on-chip spiral inductors. CICC (2002)
Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. IEEE Trans. Very Large Scale Integr. Syst. 10 (6) (2002)
Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design (2002)
Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (5) (2002)
Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. ISQED (2002)
Takashi Sato, Dennis Sylvester, Yu Cao, Chenming Hu
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling. IEEE J. Solid State Circuits 36 (10) (2001)
Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, Chenming Hu
Efficient generation of pre-silicon MOS model parameters for early circuit design. IEEE J. Solid State Circuits 36 (1) (2001)
Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. ISQED (2001)
Hajime Nakayama, Pin Su, Chenming Hu, Motoaki Nakamura, Hiroshi Komatsu, Kaneyoshi Takeshita, Yasutoshi Komatsu
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS. CICC (2001)
Yu Cao, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. CICC (2000)
Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD (2000)
Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester
Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. ICCAD (2000)
Pin Su, Samuel K. H. Fung, Stephen Tang, Fariborz Assaderaghi, Chenming Hu
BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. CICC (2000)
Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram, Chenming Hu
A simple subcircuit extension of the BSIM3v3 model for CMOS RF design. IEEE J. Solid State Circuits 35 (4) (2000)
Nick Lindert, Toshihiro Sugii, Stephen Tang, Chenming Hu
Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages. IEEE J. Solid State Circuits 34 (1) (1999)
Jone F. Chen, Jiang Tao, Peng Fang, Chenming Hu
Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates. IEEE J. Solid State Circuits 34 (3) (1999)
Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu
On Thermal Effects in Deep Sub-Micron VLSI Interconnects. DAC (1999)
Jone F. Chen, Jiang Tao, Peng Fang, Chenming Hu
Performance and reliability of asymmetric LDD devices and logic gates. CICC (1998)
Michael Orshansky, James C. Chen, Chenming Hu
A Statistical Performance Simulation Methodology for VLSI Circuits. DAC (1998)
Yuhua Cheng, Kai Chen, Kiyotaka Imai, Chenming Hu
A unified MOSFET channel charge model for device modeling in circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (8) (1998)
Kai Chen, Chenming Hu
scaling in deep submicrometer CMOS. IEEE J. Solid State Circuits 33 (10) (1998)
Dennis Sylvester, James C. Chen, Chenming Hu
Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation. IEEE J. Solid State Circuits 33 (3) (1998)
Peng Fang, Jiang Tao, Jone F. Chen, Chenming Hu
Design in hot-carrier reliability for high performance logic applications. CICC (1998)
Kai Chen, Chenming Hu
Device and technology optimizations for low power design in deep sub-micron regime. ISLPED (1997)
Kai Chen, Yuhua Cheng, Chenming Hu
Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. ISLPED (1996)
Khandker N. Quader, Eric R. Minami, Wei-Jen Huang, Ping K. Ko, Chenming Hu
Hot-carrier-reliability design guidelines for CMOS logic circuits. IEEE J. Solid State Circuits 29 (3) (1994)
Chenming Hu
Future CMOS scaling and reliability. Proc. IEEE 81 (5) (1993)
Robert H. Tu, Elyse Rosenbaum, Wilson Y. Chan, Chester C. Li, Eric Minami, Khandker Quader, Ping K. Ko, Chenming Hu
Berkeley reliability tools-BERT. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (10) (1993)
Hong June Park, Ping Keung Ko, Chenming Hu
A non-quasi-static MOSFET model for SPICE-AC analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (10) (1992)
Hong June Park, Ping Keung Ko, Chenming Hu
A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (5) (1991)
Hong June Park, Ping Keung Ko, Chenming Hu
A charge sheet capacitance model of short channel MOSFETs for SPICE. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (3) (1991)
Chenming Hu
Reliability issues of MOS and bipolar ICs. ICCD (1989)