Device and technology optimizations for low power design in deep sub-micron regime.

Kai Chen Chenming Hu

Published in: ISLPED (1997)

Keyphrases

low power
cmos technology
gate array
low cost
power consumption
ultra low power
single chip
high speed
low power consumption
nm technology
logic circuits
power reduction
vlsi architecture
power dissipation
low voltage
wireless transmission
high power
mixed signal
vlsi circuits
digital signal processing