Jean-Olivier Plouchart

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 8

Top Topics

Computing Systems

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman
Cryogenic CMOS: design considerations for future quantum computing systems. CICC (2023)
Bodhisatwa Sadhu, Arun Paidimarri, Wooram Lee, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Jean-Olivier Plouchart, Xiaoxiong Gu, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams. ISSCC (2022)
Bodhisatwa Sadhu, Arun Paidimarri, Duixian Liu, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Wooram Lee, Kevin Xiaoxiong Gu, Jean-Olivier Plouchart, Christian W. Baks, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas. IEEE J. Solid State Circuits 57 (12) (2022)
Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits 55 (6) (2020)
Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions. BCICTS (2018)
Wooram Lee, Jean-Olivier Plouchart, Caglar Ozdag, Yigit Aydogan, Mark Yeck, Alper Cabuk, Asim Kepkep, Scott K. Reynolds, Emre Apaydin, Alberto Valdes-Garcia
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C. IEEE J. Solid State Circuits 53 (9) (2018)
Jen-Chieh Hsueh, Vanessa H.-C. Chen, Jean-Olivier Plouchart
An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI. MWSCAS (2017)
Fa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, Alberto Valdes-Garcia
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information. ICCAD (2015)
Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu, Andreea Balteanu, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Daniel J. Friedman
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits. IEEE Des. Test 31 (6) (2014)
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE J. Solid State Circuits 48 (4) (2013)
Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48 (6) (2013)
Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2013)
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, A. S. Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC (2013)
Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48 (5) (2013)
Jean-Olivier Plouchart, Mihai A. T. Sanduleanu, Zeynep Toprak Deniz, Troy J. Beukema, Scott K. Reynolds, Benjamin D. Parker, Michael P. Beakes, José A. Tierno, Daniel J. Friedman
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. CICC (2012)
Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC (2012)
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC (2012)
Gokce Keskin, Jonathan E. Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. IEEE J. Solid State Circuits 46 (8) (2011)
Mihai A. T. Sanduleanu, Scott K. Reynolds, Jean-Olivier Plouchart
A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI. CICC (2011)
Jonathan E. Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi
An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC (2010)
Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC (2009)
Daeik D. Kim, Jonghae Kim, Choongyeun Cho, Jean-Olivier Plouchart, Mahender Kumar, Woo-Hyeong Lee, Ken Rim
An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS. ISSCC (2009)
Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart
Wideband mmWave CML static divider in 65nm SOI CMOS technology. CICC (2008)
Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC (2008)
Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Weipeng Li, Daihyun Lim, Robert Trzcinski, Mahender Kumar, Christine Norris, David Ahlgren
A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS. ISSCC (2007)
Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski
Statistical Framework for Technology-Model-Product Co-Design and Convergence. DAC (2007)
Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. ISQED (2007)
Daihyun Lim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daeik D. Kim, Robert Trzcinski, Duane S. Boning
Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS. ISSCC (2007)
Jean-Olivier Plouchart, Jonghae Kim, Victor Karam, Robert Trzcinski, Jeff Gross
Performance Variations of a 66GHz Static CML Divider in 90nm CMOS. ISSCC (2006)
Daeik D. Kim, Choongyeun Cho, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski, David Ahlgren
CMOS Mixed-Signal Circuit Process Variation Sensitivity Characterization for Yield Improvement. CICC (2006)
Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer
Design and manufacturability aspect of SOI CMOS RFICs. CICC (2004)
Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert A. Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner
A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology. IEEE J. Solid State Circuits 39 (9) (2004)
Neric H. W. Fong, Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Garry Tarr
A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology. IEEE J. Solid State Circuits 39 (5) (2004)
Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi, Lawrence F. Wagner, Kun Wu, Naftali E. Lustig, Shreesh Narasimha, Patricia O'Neil, Nghia Phan, Michael Rohn, James Strom, David M. Friend, Stephen V. Kosonocky, Daniel R. Knebel, Suhwan Kim, Keith A. Jenkins, Michel M. Rivier
Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. IBM J. Res. Dev. 47 (5-6) (2003)
Jean-Olivier Plouchart, Jonghae Kim, Hector Recoules, Noah Zamdmer, Yue Tan, Melanie Sherony, Asit Ray, Lawrence F. Wagner
A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology. ISLPED (2003)
Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner
A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate. ISLPED (2003)
Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Liang-Hung Lu, Melanie Sherony, Yue Tan, Robert Groves, Robert Trzcinski, Mohamed Talbi, Asit Ray, Lawrence F. Wagner
A 4-91 GHz distributed amplifier in a standard 0.12 μm SOI CMOS microprocessor technology. CICC (2003)
Yu Cao, Robert A. Groves, Xuejue Huang, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Tsu-Jae King, Chenming Hu
Frequency-independent equivalent-circuit model for on-chip spiral inductors. IEEE J. Solid State Circuits 38 (3) (2003)
Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, N. Garry Tarr
Design of wide-band CMOS VCO for multiband wireless LAN applications. IEEE J. Solid State Circuits 38 (8) (2003)
Jean-Olivier Plouchart, Jonghae Kim, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Mohamed Talbi, Asit Ray, Lawrence F. Wagner
A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology. ESSCIRC (2003)
Yu Cao, Robert A. Groves, Noah Zamdmer, Jean-Olivier Plouchart, Richard A. Wachnik, Xuejue Huang, Tsu-Jae King, Chenming Hu
Frequency-independent equivalent circuit model for on-chip spiral inductors. CICC (2002)
Neric H. W. Fong, Jean-Olivier Plouchart, Noah Zamdmer, Duixian Liu, Lawrence F. Wagner, Calvin Plett, Gerry Tarr
A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS. CICC (2002)
Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. Proc. IEEE 88 (10) (2000)
Jean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer
A 5.2 GHz 3.3 V I/Q SiGe RF transceiver. CICC (1999)