A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.

Jean-Olivier Plouchart Mark A. Ferriss A. S. Natarajan Alberto Valdes-Garcia Bodhisatwa Sadhu Alexander V. Rylyakov Benjamin D. Parker Michael P. Beakes Aydin Babakhani Soner Yaldiz Larry T. Pileggi Ramesh Harjani Scott K. Reynolds José A. Tierno Daniel J. Friedman

Published in: IEEE Trans. Circuits Syst. I Regul. Pap. (2013)

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