An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
Mark A. FerrissJean-Olivier PlouchartArun NatarajanAlexander V. RylyakovBenjamin D. ParkerAydin BabakhaniSoner YaldizBodhisatwa SadhuAlberto Valdes-GarciaJosé A. TiernoDaniel J. FriedmanPublished in: VLSIC (2012)