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An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

Mark A. FerrissJean-Olivier PlouchartArun NatarajanAlexander V. RylyakovBenjamin D. ParkerAydin BabakhaniSoner YaldizBodhisatwa SadhuAlberto Valdes-GarciaJosé A. TiernoDaniel J. Friedman
Published in: VLSIC (2012)
Keyphrases
  • silicon on insulator
  • high speed
  • shortest path
  • closed form
  • circuit design
  • camera calibration
  • power consumption
  • cmos technology
  • multiple views
  • focal length
  • ibm power processor