Sangyeun Cho

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 21

Top Topics

Foreseeable Future

Top Venues

IEEE Trans. Computers

Publications

Jisoo Kim, Mungyu Bae, Yeonsung Chu, Moon Chan Park, Dongwon Park, Dawoon Jung, Sangyeun Cho
Self-Encrypting Drive Evolving Toward Multitenant Cloud Computing. Computer 57 (2) (2024)
Myoungwon Oh, Sungmin Lee, Samuel Just, Youngjin Yu, Duck-Ho Bae, Sage A. Weil, Sangyeun Cho, Heon Y. Yeom
TiDedup: A New Distributed Deduplication Architecture for Ceph. USENIX Annual Technical Conference (2023)
Youjip Won, Jaemin Jung, Gyeongyeol Choi, Joontaek Oh, Seongbae Son, Joo Young Hwang, Sangyeun Cho
Barrier-Enabled IO Stack for Flash Storage. FAST (2018)
Eunhee Rho, Kanchan Joshi, Seung-Uk Shin, Nitesh Jagadeesh Shetty, Joo Young Hwang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong
FStream: Managing Flash Streams in the File System. FAST (2018)
Duck-Ho Bae, Insoon Jo, Youra Choi, Joo Young Hwang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong
2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State Drives. ISCA (2018)
Youjip Won, Joontaek Oh, Jaemin Jung, Gyeongyeol Choi, Seongbae Son, Joo Young Hwang, Sangyeun Cho
Bringing Order to Chaos: Barrier-Enabled I/O Stack for Flash Storage. ACM Trans. Storage 14 (3) (2018)
Wooseong Cheong, Chanho Yoon, Seonghoon Woo, Kyuwook Han, Daehyun Kim, Chulseung Lee, Youra Choi, Shine Kim, Dongku Kang, Geunyeong Yu, Jaehong Kim, Jaechun Park, Ki-Whan Song, Ki-Tae Park, Sangyeun Cho, Hwaseok Oh, Daniel D. G. Lee, Jin-Hyeok Choi, Jaeheon Jeong
A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time. ISSCC (2018)
Youjip Won, Jaemin Jung, Gyeongyeol Choi, Joontaek Oh, Seongbae Son, Joo Young Hwang, Sangyeun Cho
Barrier Enabled IO Stack for Flash Storage. CoRR (2017)
Min-Kwan Kee, Hong-Yeol Lim, Gi-Ho Park, Sangyeun Cho
An analytical model based on performance demand of workload for energy-efficient heterogeneous multicore systems. J. Parallel Distributed Comput. 100 (2017)
Jonghyun Bae, Hakbeom Jang, Wenjing Jin, Jun Heo, Jaeyoung Jang, Joo Young Hwang, Sangyeun Cho, Jae W. Lee
Jointly optimizing task granularity and concurrency for in-memory mapreduce frameworks. IEEE BigData (2017)
Boncheol Gu, Andre S. Yoon, Duck-Ho Bae, Insoon Jo, Jinyoung Lee, Jonghyun Yoon, Jeong-Uk Kang, Moonsang Kwon, Chanho Yoon, Sangyeun Cho, Jaeheon Jeong, Duckhyun Chang
Biscuit: A Framework for Near-Data Processing of Big Data Workloads. ISCA (2016)
Insoon Jo, Duck-Ho Bae, Andre S. Yoon, Jeong-Uk Kang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong
YourSQL: A High-Performance Database System Leveraging In-Storage Computing. Proc. VLDB Endow. 9 (12) (2016)
Sungyong Seo, Youngjin Cho, Youngkwang Yoo, Otae Bae, Jaegeun Park, Heehyun Nam, Sunmi Lee, Yongmyung Lee, Seungdo Chae, Moonsang Kwon, Jin-Hyeok Choi, Sangyeun Cho, Jaeheon Jeong, Duckhyun Chang
Design and implementation of a mobile storage leveraging the DRAM interface. HPCA (2016)
Rakan Maddah, Sangyeun Cho, Rami G. Melhem
Symbol Shifting: Tolerating More Faults in PCM Blocks. IEEE Trans. Computers 65 (7) (2016)
Sungchan Kim, Hyunok Oh, Chanik Park, Sangyeun Cho, Sang-Won Lee, Bongki Moon
In-storage processing of database scans and joins. Inf. Sci. 327 (2016)
Sangyeun Cho
Fast memory and storage architectures for the big data era. A-SSCC (2015)
Sangyeun Cho
Recent advances in flash solutions. ICDE Workshops (2015)
Changman Lee, Dongho Sim, Joo Young Hwang, Sangyeun Cho
F2FS: A New File System for Flash Storage. FAST (2015)
Rakan Maddah, Rami G. Melhem, Sangyeun Cho
RDIS: Tolerating Many Stuck-At Faults in Resistive Memory. IEEE Trans. Computers 64 (3) (2015)
Sangyeun Cho, Sanghoan Chang, Insoon Jo
The solid-state drive technology, today and tomorrow. ICDE (2015)
Fei Yang, Kun Dou, Siyu Chen, Mengwei Hou, Jeong-Uk Kang, Sangyeun Cho
Optimizing NoSQL DB on Flash: A Case Study of RocksDB. UIC/ATC/ScalCom (2015)
Jeong-Uk Kang, Jeeseok Hyun, Hyunjoo Maeng, Sangyeun Cho
The Multi-streamed Solid-State Drive. HotStorage (2014)
Seungjae Baek, Daeyeon Son, Dongwoo Kang, Jongmoo Choi, Sangyeun Cho
Design space exploration of an NVM-based memory hierarchy. ICCD (2014)
Seungjae Baek, Sangyeun Cho, Rami G. Melhem
Refresh Now and Then. IEEE Trans. Computers 63 (12) (2014)
Musfiq Rahman, Bruce R. Childers, Sangyeun Cho
COMeT+: Continuous Online Memory Testing with Multi-Threading Extension. IEEE Trans. Computers 63 (7) (2014)
Sangyeun Cho
Keynote: "Flashing the roads ahead". NVMSA (2014)
Socrates Demetriades, Sangyeun Cho
Stash directory: A scalable directory for many-core coherence. HPCA (2014)
Rakan Maddah, Sangyeun Cho, Rami G. Melhem
Data Dependent Sparing to Manage Better-Than-Bad Blocks. IEEE Comput. Archit. Lett. 12 (2) (2013)
Rakan Maddah, Sangyeun Cho, Rami G. Melhem
Power of One Bit: Increasing Error Correction Capability with Data Inversion. PRDC (2013)
Ju-Young Jung, Sangyeun Cho
Memorage: emerging persistent RAM based malleable main memory and storage architecture. ICS (2013)
Kiyeon Lee, Sangyeun Cho
Accurately modeling superscalar processor performance with reduced trace. J. Parallel Distributed Comput. 73 (4) (2013)
Sangyeun Cho, Chanik Park, Hyunok Oh, Sungchan Kim, Youngmin Yi, Gregory R. Ganger
Active disk meets flash: a case for intelligent SSDs. ICS (2013)
Andrew Conn, Joseph V. Cavanaugh, Sangyeun Cho
A Theoretical Design for SSD Texture Storage. ICPP Workshops (2012)
Socrates Demetriades, Sangyeun Cho
Predicting Coherence Communication by Tracking Synchronization Points at Run Time. MICRO (2012)
Zitao Liu, Sangyeun Cho
Characterizing Machines and Workloads on a Google Cluster. ICPP Workshops (2012)
Rami G. Melhem, Rakan Maddah, Sangyeun Cho
RDIS: A recursively defined invertible set scheme to tolerate multiple stuck-at faults in resistive memory. DSN (2012)
Kiyeon Lee, Moo-Kyoung Chung, Soojung Ryu, Yeon-Gon Cho, Sangyeun Cho
Design and evaluation of a four-port data cache for high instruction level parallelism reconfigurable processors. ICCD (2012)
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
C-AMTE: A location mechanism for flexible cache management in chip multiprocessors. J. Parallel Distributed Comput. 71 (6) (2011)
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
DEFCAM: A design and evaluation framework for defect-tolerant cache memories. ACM Trans. Archit. Code Optim. 8 (3) (2011)
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches. HiPEAC (2011)
Ju-Young Jung, Sangyeun Cho
Dynamic co-management of persistent RAM main memory and storage resources. Conf. Computing Frontiers (2011)
Sangyeun Cho, Socrates Demetriades
MAESTRO: Orchestrating predictive resource management in future multicore systems. AHS (2011)
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
CloudCache: Expanding and shrinking private caches. HPCA (2011)
Musfiq Rahman, Bruce R. Childers, Sangyeun Cho
COMeT: Continuous Online Memory Test. PRDC (2011)
Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem
Advanced hashing schemes for packet forwarding using set associative memory architectures. J. Parallel Distributed Comput. 71 (1) (2011)
Lei Jin, Sangyeun Cho
Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse. IEEE Trans. Computers 60 (4) (2011)
Sungchan Kim, Hyunok Oh, Chanik Park, Sangyeun Cho, Sang-Won Lee
Fast, Energy Efficient Scan inside Flash Memory. ADMS@VLDB (2011)
Kiyeon Lee, Sangyeun Cho
In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. MASCOTS (2011)
Michel Hanna, Sangyeun Cho, Rami G. Melhem
A Novel Scalable IPv6 Lookup Scheme Using Compressed Pipelined Tries. Networking (1) (2011)
Ju-Young Jung, Sangyeun Cho
PRISM: Zooming in persistent RAM storage behavior. ISPASS (2011)
Michael Moeng, Sangyeun Cho, Rami G. Melhem
Scalable Multi-cache Simulation Using GPUs. MASCOTS (2011)
Taecheol Oh, Kiyeon Lee, Sangyeun Cho
An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. MASCOTS (2011)
Socrates Demetriades, Sangyeun Cho
BarrierWatch: characterizing multithreaded workloads across and within program-defined epochs. Conf. Computing Frontiers (2011)
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
An intra-tile cache set balancing scheme. PACT (2010)
Musfiq Rahman, Bruce R. Childers, Sangyeun Cho
StealthWorks: Emulating Memory Errors. RV (2010)
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
PERFECTORY: A Fault-Tolerant Directory Memory Architecture. IEEE Trans. Computers 59 (5) (2010)
Sangyeun Cho, Rami G. Melhem
On the Interplay of Parallelization, Program Performance, and Energy Consumption. IEEE Trans. Parallel Distributed Syst. 21 (3) (2010)
Brian Wongchaowart, Marian Kamal Iskander, Sangyeun Cho
A content-aware block placement algorithm for reducing PRAM storage bit writes. MSST (2010)
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
StimulusCache: Boosting performance of chip multiprocessors with excess cache. HPCA (2010)
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors. IEEE Comput. Archit. Lett. 9 (1) (2010)
Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. Softw. Pract. Exp. 40 (3) (2010)
Lei Jin, Sangyeun Cho
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. PACT (2009)
Sangyeun Cho, Hyunjin Lee
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance. MICRO (2009)
Kiyeon Lee, Shayne Evans, Sangyeun Cho
Accurately approximating superscalar processor performance from traces. ISPASS (2009)
Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem
Progressive hashing for packet processing using set associative memory. ANCS (2009)
Sangyeun Cho, Lory Al Moakar
Augmented FIFO Cache Replacement Policies for Low-Power Embedded Processors. J. Circuits Syst. Comput. 18 (6) (2009)
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
Dynamic cache clustering for chip multiprocessors. ICS (2009)
Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. ISVLSI (2009)
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors. HiPEAC (2009)
Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem
CHAP: Enabling Efficient Hardware-Based Multiple Hash Schemes for IP Lookup. Networking (2009)
Sangyeun Cho, Tao Li, Onur Mutlu
Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems. IEEE Micro 28 (3) (2008)
Jongbae Kim, Sangyeun Cho, Seung-Jae Kim
Preliminary studies to develop a ubiquitous computing and health-monitoring system for wheelchair users. BODYNETS (2008)
Lei Jin, Sangyeun Cho
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches. ICPP (2008)
Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. ICPP (2008)
Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Daihyun Lim, Sangyeun Cho
Early prediction of product performance and yield via technology benchmark. CICC (2008)
Sangyeun Cho, Rami G. Melhem
Corollaries to Amdahl's Law for Energy. IEEE Comput. Archit. Lett. 7 (1) (2008)
Socrates Demetriades, Michel Hanna, Sangyeun Cho, Rami G. Melhem
An Efficient Hardware-Based Multi-hash Scheme for High Speed IP Lookup. Hot Interconnects (2008)
Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. ISPASS (2007)
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
Exploring the interplay of yield, area, and performance in processor caches. ICCD (2007)
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
Performance of Graceful Degradation for Cache Faults. ISVLSI (2007)
Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. ISQED (2007)
Sangyeun Cho
I-cache multi-banking and vertical interleaving. ACM Great Lakes Symposium on VLSI (2007)
Sangyeun Cho, Lei Jin, Kiyeon Lee
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. RTCSA (2007)
Lei Jin, Sangyeun Cho
Reducing cache traffic and energy with macro data load. ISLPED (2006)
Sangyeun Cho, Lei Jin
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. MICRO (2006)
Lei Jin, Hyunjin Lee, Sangyeun Cho
A flexible data to L2 cache mapping approach for future multicore processors. Memory System Performance and Correctness (2006)
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong
-Based Systems. ICCD (2001)
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
A High-Bandwidth Memory Pipeline for Wide Issue Processors. IEEE Trans. Computers 50 (7) (2001)
Sangyeun Cho, Jinseok Kong, Gyungho Lee
Coherence and Replacement Protocol of DICE-A Bus-Based COMA Multiprocessor. J. Parallel Distributed Comput. 57 (1) (1999)
Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney
Design of a bus-based shared-memory multiprocessor DICE. Microprocess. Microsystems 22 (7) (1999)
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
Access Region Locality for High-Bandwidth Processor Memory System Design. MICRO (1999)
Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. ISCA (1999)
Sangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia Zheng, Stephen J. Schwinn, Xin Wang, Qing Zhao, Zhiyuan Li, David J. Lilja, Pen-Chung Yew
High-Level Information - An Approach for Integrating Front-End and Back-End Compilers. ICPP (1998)
Sangyeun Cho, Jinseok Kong, Gyungho Lee
On timing constraints of snooping in a bus-based COMA multiprocessor. Microprocess. Microsystems 21 (5) (1998)
Sangyeun Cho, Gyungho Lee
Reducing Coherence Overhead in Shared-Bus Multiprocessors. Euro-Par, Vol. II (1996)
Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney
Global Bus Design of a Bus-Based COMA Multiprocessor DICE. ICCD (1996)