Gi-Ho Park

ORCID

Publication Activity (10 Years)

Years Active: 1996-2023
Publications (10 Years): 10

Top Venues

IEICE Electron. Express

Comput. J.

3DIC

IEEE Micro

Georgia Institute of Technology, Atlanta, GA, USA (PHD)

Education History

Georgia Institute of Technology, Atlanta, GA, USA

PHD

Publications

Min-Kwan Kee, Chiwon Han, Gi-Ho Park
An Integrated Solution to Improve Performance of In-Memory Data Caching With an Efficient Item Retrieving Mechanism and a Near-Memory Accelerator. IEEE Access 11 (2023)
Jaeung Lee, Chiwon Han, Kyungeun Kim, Gi-Ho Park, Jin Tae Kwak
CaMeL-Net: Centroid-aware metric learning for efficient multi-class cancer classification in pathology images. Comput. Methods Programs Biomed. 241 (2023)
Min-Kwan Kee, Gi-Ho Park
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices. ACM Trans. Design Autom. Electr. Syst. 27 (5) (2022)
Duk-Jun Bang, Min-Kwan Kee, Hong-Yeol Lim, Gi-Ho Park
An adaptive cache replacement policy based on fine-grain reusability monitor. IEICE Electron. Express 15 (2) (2018)
Min-Kwan Kee, Seung-Jin Lee, Hyun-Su Seon, Jongsung Lee, Gi-Ho Park
Intelligence Boosting Engine (IBE): A hardware accelerator for processing sensor fusion and machine learning algorithm for a sensor hub SoC. COOL Chips (2017)
Seung-Jin Lee, Min-Kwan Kee, Gi-Ho Park
Sensor data compression and power management scheme for low power sensor hub. IEICE Electron. Express 14 (23) (2017)
Min-Kwan Kee, Hong-Yeol Lim, Gi-Ho Park, Sangyeun Cho
An analytical model based on performance demand of workload for energy-efficient heterogeneous multicore systems. J. Parallel Distributed Comput. 100 (2017)
Ju Hee Choi, Gi-Ho Park
NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors. IEEE Trans. Parallel Distributed Syst. 28 (10) (2017)
Hong-Yeol Lim, Gi-Ho Park
Cooperative cache memory (CCM) based on the performance efficiency for 3D stacked memory system. IEICE Electron. Express 13 (12) (2016)
Ju Hee Choi, Gi-Ho Park
Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture. Comput. J. 59 (5) (2016)
Hyojong Kim, Hong-Yeol Lim, Dilan Manatunga, Hyesoon Kim, Gi-Ho Park
Accelerating Application Start-up with Nonvolatile Memory in Android Systems. IEEE Micro 35 (1) (2015)
Sung-In Jang, Su-Kyung Yoon, Kihyun Park, Gi-Ho Park, Shin-Dug Kim
Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory. Comput. J. 58 (11) (2015)
Ju Hee Choi, Gi-Ho Park
Adaptive replacement policy for hybrid cache architecture. IEICE Electron. Express 11 (22) (2014)
Hong-Yeol Lim, Min-Kwan Kee, Gi-Ho Park
Phase detection based data prefetching for utilizing memory bandwidth of 3D integrated circuits. 3DIC (2013)
Hong-Yeol Lim, Gi-Ho Park
An adaptive L2 cache prefetching mechanism for effective exploitation of abundant memory bandwidth of 3-D IC technology. IEICE Electron. Express 10 (16) (2013)
Hong-Yeol Lim, Gi-Ho Park
Versatile stream buffer architecture to exploit the high memory bandwidth of 3-D IC technology. IEICE Electron. Express 10 (4) (2013)
Byung-Min Lee, Gi-Ho Park
Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM. ISOCC (2012)
Hong-Yeol Lim, Gi-Ho Park
Adaptive prefetching scheme for exploiting massive memory bandwidth of 3-D IC technology. 3DIC (2011)
Gunok Jung, Gi-Ho Park, Ukrae Cho, Jae-Cheol Son
Fully digital clock frequency doubler. IEICE Electron. Express 7 (6) (2010)
Jung-Wook Park, Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim, Charles C. Weems
An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing. J. Parallel Distributed Comput. 70 (11) (2010)
Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, Tae-Jin Kim, Sung-Bae Park
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC). Microprocess. Microsystems 34 (2-4) (2010)
Jung-Wook Park, Gi-Ho Park, Charles C. Weems, Shin-Dug Kim
Sub-grouped superblock management for high-performance flash storages. IEICE Electron. Express 6 (6) (2009)
Jung-Wook Park, Seung-Ho Park, Gi-Ho Park, Shin-Dug Kim
An integrated mapping table for hybrid FTL with fault-tolerant address cache. IEICE Electron. Express 6 (7) (2009)
Gi-Ho Park, Jung-Wook Park, Hoi-Jin Lee, Gunok Jung, Sung-Bae Park, Shin-Dug Kim
A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache. IEICE Trans. Electron. (4) (2009)
Gi-Ho Park, Jung-Wook Park, Gunok Jung, Shin-Dug Kim
Low-Power Embedded Processor Design Using Branch Direction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Gunok Jung, Chunghee Kim, Kyoungkuk Chae, Gi-Ho Park, Sung-Bae Park
Power and Skew Aware Point Diffusion Clock Network. IEICE Trans. Electron. (11) (2008)
Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim
Cooperative Cache System: A Low Power Cache System for Embedded Processors. IEICE Trans. Electron. (4) (2007)
Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, WooKyeong Jeong, Tae-Jin Kim, Sung-Bae Park
Performance monitor unit design for an AXI-based multi-core SoC platform. SAC (2007)
Jung-Min Park, Jung-Wook Park, Cheong-Ghil Kim, Gi-Ho Park, Shin-Dug Kim
An efficient scheme for parallelizing fast search algorithm on SIMD architecture in H.264/AVC. PDCS (2007)
Sung Woo Chung, Gi-Ho Park, Hyo-Joong Suh, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Sung-Bae Park
Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator. Microprocess. Microsystems 30 (3) (2006)
Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, Sung-Bae Park
Practice and Experience of an Embedded Processor Core Modeling. HPCC (2006)
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
A deterministic way-prediction scheme using power-aware replacement policy. Microprocess. Microsystems 30 (4) (2006)
Hoon-Mo Yang, Gi-Ho Park, Shin-Dug Kim
Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference (2006)
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities. J. Syst. Archit. 51 (2) (2005)
Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure. ICCD (2004)
Sung Woo Chung, Gi-Ho Park, Sung-Bae Park
A Low-Power Branch Predictor for Embedded Processors. IEICE Trans. Inf. Syst. (9) (2004)
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
Dynamic and selective low power data TLB system. Microprocess. Microsystems 28 (3) (2004)
Sung Woo Chung, Gi-Ho Park, Sung-Bae Park
A Low-Power Tournament Branch Predictor. IEICE Trans. Inf. Syst. (7) (2004)
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications. PDP (2003)
Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
Appliaction-Specific Data Cache Systems. CATA (2003)
Jung-Hoon Lee, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
A selective filter-bank TLB system. ISLPED (2003)
Jin-Hyuck Choi, Jung-Hoon Lee, Gi-Ho Park, Shin-Dug Kim
An Advanced Filtering TLB for Low Power Consumption. SBAC-PAD (2002)
Gi-Ho Park, Kil-Whan Lee, Jae-Hyuk Lee, Tack-Don Han, Shin-Dug Kim
A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure. LCTES (2000)
Gi-Ho Park, Kil-Whan Lee, Tack-Don Han, Shin-Dug Kim
A Dual Data Cache System to Reflect the Principle of Locality Effectively. PDPTA (2000)
Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, Shin-Dug Kim, Sung-Bong Yang
Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors. J. Syst. Archit. 44 (9-10) (1998)
Oh-Young Kwon, Gi-Ho Park, Tack-Don Han
A compiler optimization to reduce execution time of loop nest. SIGARCH Comput. Archit. News 24 (1) (1996)

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Publication Activity (10 Years)

Top Topics

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Gi-Ho Park