A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices.
Min-Kwan KeeGi-Ho ParkPublished in: ACM Trans. Design Autom. Electr. Syst. (2022)
Keyphrases
- low power
- single chip
- low cost
- low power consumption
- vlsi architecture
- machine learning
- high speed
- power consumption
- embedded systems
- digital signal processing
- signal processor
- logic circuits
- gate array
- mixed signal
- real time
- power reduction
- field programmable gate array
- power dissipation
- cmos technology
- high power
- hardware and software
- wireless transmission
- vlsi circuits
- cmos image sensor
- ultra low power
- parallel implementation
- computer systems
- storage devices
- image sensor
- computer architecture
- efficient implementation
- low complexity