A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology.
Jean-Olivier PlouchartJonghae KimNoah ZamdmerMelanie SheronyYue TanMeeyoung YoonMohamed TalbiAsit RayLawrence F. WagnerPublished in: ESSCIRC (2003)
Keyphrases
- cmos technology
- power dissipation
- silicon on insulator
- clock frequency
- power consumption
- low power
- spl times
- high speed
- low voltage
- parallel processing
- digital signal processing
- mixed signal
- low cost
- energy efficiency
- design methodology
- frequency band
- power management
- image sensor
- real time
- pattern recognition
- computer vision
- neural network