Yogesh Singh Chauhan

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 57

Top Topics

Quantum Computing

Industry Standard

Top Venues

Microelectron. J.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction. IRPS (2024)
Mohammad Zaid, Ahtisham Pampori, Mohammad Sajid Nazir, Yogesh Singh Chauhan
GaN-based wide-band high-efficiency power amplifier with multi harmonic resonance. Microelectron. J. 145 (2024)
Mohammad Zaid, Mohammad Sajid Nazir, Raghavendra Dangi, Yogesh Singh Chauhan
Design and experimental validation of class-F-1 GaN power amplifier using a compact harmonic control unit. Microelectron. J. 149 (2024)
Anirban Kar, Florian Klemme, Yogesh Singh Chauhan, Hussam Amrouch
On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth Analysis from Transistors to Full Processor. IRPS (2024)
Mohammad Zaid, Purnima Kumari, Ahtisham Pampori, Mohammad Sajid Nazir, Umakant Goyal, Meena Mishra, Yogesh Singh Chauhan
Optimizing Low Noise Amplifiers: A Two-Stage Approach for Improved Noise Figure and Stability. IEEE Access 12 (2024)
Swetaki Chatterjee, Nikhil Rangarajan, Satwik Patnaik, Dinesh Rajasekharan, Ozgur Sinanoglu, Yogesh Singh Chauhan
FerroCoin: Ferroelectric Tunnel Junction-Based True Random Number Generator. IEEE Trans. Emerg. Top. Comput. 11 (2) (2023)
Shubham Kumar, Yogesh Singh Chauhan, Hussam Amrouch
Invited Paper: Ultra-Efficient Edge AI Using FeFET-based Monolithic 3D Integration. ICCAD (2023)
Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. CoRR (2023)
Liu Liu, Shubham Kumar, Simon Thomann, Yogesh Singh Chauhan, Hussam Amrouch, Xiaobo Sharon Hu
Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs. CoRR (2023)
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs. IEEE Open J. Circuits Syst. 4 (2023)
Shubham Kumar, Paul R. Genssler, Somaya Mansour, Yogesh Singh Chauhan, Hussam Amrouch
Frontiers in AI Acceleration: From Approximate Computing to FeFET Monolithic 3D Integration. VLSI-SoC (2023)
Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing. DRC (2023)
Amol D. Gaidhane, Raghvendra Dangi, Shubham Sahay, Amit Verma, Yogesh Singh Chauhan
A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (5) (2023)
Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Yogesh Singh Chauhan, Hussam Amrouch
Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (7) (2023)
Girish Pahwa, Ayushi Sharma, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu
Robust Compact Model of High-Voltage MOSFET's Drift Region. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Victor M. van Santen, Marcel Walter, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Robert Wille, Hussam Amrouch
Design Automation for Cryogenic CMOS Circuits. DAC (2023)
Dinesh Rajasekharan, Nikhil Rangarajan, Satwik Patnaik, Ozgur Sinanoglu, Yogesh Singh Chauhan
SCANet: Securing the Weights With Superparamagnetic-MTJ Crossbar Array Networks. IEEE Trans. Neural Networks Learn. Syst. 34 (9) (2023)
Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (8) (2023)
Neha Bajpai, Paramita Maity, Manish Shah, Amitava Das, Yogesh Singh Chauhan
An Ultra-Low Noise Figure and Multi-Band Re-Configurable Low Noise Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (3) (2023)
Anirban Kar, Swapna Sarker, Avirup Dasgupta, Yogesh Singh Chauhan
Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes. DRC (2022)
Dinesh Rajasekharan, Amol D. Gaidhane, Amit Ranjan Trivedi, Yogesh Singh Chauhan
Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (7) (2022)
Shubham Kumar, Swetaki Chatterjee, Chetan K. Dabhi, Hussam Amrouch, Yogesh Singh Chauhan
A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology. NEWCAS (2022)
Sami Salamin, Georgios Zervakis, Florian Klemme, Hammam Kattan, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU. IEEE Trans. Computers 71 (4) (2022)
Wajid Manzoor, Aloke K. Dutta, Yogesh Singh Chauhan
Analytical approximation of surface potential and analysis of C-V characteristics of bulk MOSFETs at cryogenic temperatures. Microelectron. J. 129 (2022)
Neha Bajpai, Yogesh Singh Chauhan
A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier. VDAT (2022)
Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. VLSI Technology and Circuits (2022)
Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Paul R. Genssler, Yogesh Singh Chauhan, Hussam Amrouch
Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing. VLSI-SoC (2022)
Shubham Kumar, Swetaki Chatterjee, Chetan Kumar Dabhi, Hussam Amrouch, Yogesh Singh Chauhan
Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing. ISCAS (2022)
Raghvendra Dangi, Ahtisham Pampori, Pragya Kushwaha, Ekta Yadav, Santanu Sinha, Yogesh Singh Chauhan
A width-scalable SPICE compact model for GaN HEMTs including self-heating effect. DRC (2022)
Shivendra S. Parihar, Jun Z. Huang, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan
Self-Heating characterization and modeling of 5nm technology node FinFETs. DRC (2022)
Om Prakash, Chetan K. Dabhi, Yogesh Singh Chauhan, Hussam Amrouch
Transistor Self-Heating: The Rising Challenge for Semiconductor Testing. VTS (2021)
Sami Salamin, Georgios Zervakis, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (10) (2021)
Amol D. Gaidhane, Amit Verma, Yogesh Singh Chauhan
Study of multi-domain switching dynamics in negative capacitance FET using SPICE model. Microelectron. J. 115 (2021)
Georgios Zervakis, Iraklis Anagnostopoulos, Sami Salamin, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
Impact of NCFET on Neural Network Accelerators. IEEE Access 9 (2021)
Guilherme Paim, Georgios Zervakis, Girish Pahwa, Yogesh Singh Chauhan, Eduardo Antonio Cesar da Costa, Sergio Bampi, Jörg Henkel, Hussam Amrouch
On the Resiliency of NCFET Circuits Against Voltage Over-Scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (4) (2021)
Neha Bajpai, Ahtisham Pampori, Paramita Maity, Manish Shah, Amitava Das, Yogesh Singh Chauhan
A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules. IEEE Access 9 (2021)
Ravi Goel, Weike Wang, Yogesh Singh Chauhan
Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation. Microelectron. J. 110 (2021)
Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch
Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET). CoRR (2020)
Dinesh Rajasekharan, Pragya Kushwaha, Yogesh Singh Chauhan
Associative processing using negative capacitance FDSOI transistor for pattern recognition. Microelectron. J. 104 (2020)
Florian Klemme, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch
Cell Library Characterization using Machine Learning for Design Technology Co-Optimization. ICCAD (2020)
Johann Knechtel, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Yogesh Singh Chauhan, Jörg Henkel, Ozgur Sinanoglu, Hussam Amrouch
Power Side-Channel Attacks in Negative Capacitance Transistor. IEEE Micro 40 (6) (2020)
Hussam Amrouch, Victor M. van Santen, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
NCFET to Rescue Technology Scaling: Opportunities and Challenges. ASP-DAC (2020)
Govind Bajpai, Aniket Gupta, Om Prakash, Girish Pahwa, Jörg Henkel, Yogesh Singh Chauhan, Hussam Amrouch
Impact of Radiation on Negative Capacitance FinFET. IRPS (2020)
Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Chetan K. Dabhi, Florian Klemme, Om Prakash, Yogesh Singh Chauhan
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Sami Salamin, Martin Rapp, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
NCFET-Aware Voltage Scaling. ISLPED (2019)
Martin Rapp, Sami Salamin, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel
Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores. DAC (2019)
Dinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh Chauhan
Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications. VLSI Design (2019)
Chetan Gupta, Ravi Goel, Harshit Agarwal, Chenming Hu, Yogesh Singh Chauhan
BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design. CICC (2019)
Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Jörg Henkel, Yogesh Singh Chauhan
Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance. IEEE Access 6 (2018)
Sourabh Khandelwal, Yogesh Singh Chauhan, Jason Hodges, Sayed Ali Albahrani
Non-Linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model (Invited). BCICTS (2018)
Avirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Ethirajan Tamilmani, Chenming Hu, Yogesh Singh Chauhan
Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs. VLSI Design (2017)
Chandan Yadav, Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Yogesh Singh Chauhan
Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence. VLSI Design (2016)
Pragya Kushwaha, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan
Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG. Microelectron. J. 56 (2016)
Girish Pahwa, Tapas Dutta, Amit Agarwal, Yogesh Singh Chauhan
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach. ESSCIRC (2016)
Chandan Yadav, Amit Agarwal, Yogesh Singh Chauhan
Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor. VLSI Design (2016)
Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (8) (2015)
Juan Pablo Duarte, Sourabh Khandelwal, Aditya Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan
BSIM-CMG: Standard FinFET compact model for advanced circuit design. ESSCIRC (2015)
Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Harshit Agarwal, Yogesh Singh Chauhan, Richard Q. Williams
BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF Applications. VLSI Design (2014)
Navid Paydavosi, Sriramkumar Venugopalan, Yogesh Singh Chauhan, Juan Pablo Duarte, Srivatsava Jandhyala, Ali M. Niknejad, Chenming Hu
BSIM - SPICE Models Enable FinFET and UTB IC Designs. IEEE Access 1 (2013)
Yogesh Singh Chauhan, Sriramkumar Venugopalan, Navid Paydavosi, Pragya Kushwaha, Srivatsava Jandhyala, Juan Pablo Duarte, Shantanu Agnihotri, Chandan Yadav, Harshit Agarwal, Ali M. Niknejad, Chenming Calvin Hu
BSIM compact MOSFET models for SPICE simulation. MIXDES (2013)
Maria-Anna Chalkiadaki, Anurag Mangla, Christian C. Enz, Yogesh Singh Chauhan, Mohammed Ahosan Ul Karim, Sriramkumar Venugopalan, Ali M. Niknejad, Chenming Hu
Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology. ESSCIRC (2012)
Yogesh Singh Chauhan, Sriramkumar Venugopalan, Mohammed A. Karim, Sourabh Khandelwal, Navid Paydavosi, Pankaj Thakur, Ali M. Niknejad, Chenming Hu
BSIM - Industry standard compact MOSFET models. ESSCIRC (2012)
Shyam Parthasarathy, Amit Ranjan Trivedi, Saurabh Sirohi, Robert A. Groves, Michael Olsen, Yogesh Singh Chauhan, Michael Carroll, Dan Kerr, Ali Tombak, Phil Mason
RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications. VLSI Design (2010)
Yogesh Singh Chauhan, Dimitrios Tsamados, Nicolas Abelé, Christoph Eggimann, Michel J. Declercq, Adrian M. Ionescu
Compact Modeling of Suspended Gate FET. VLSI Design (2008)
Yogesh Singh Chauhan, François Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling. VLSI Design (2007)
Dimitrios Tsamados, Yogesh Singh Chauhan, Christoph Eggimann, Adrian Mihai Ionescu
Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications. Nano-Net (2007)
Yogesh Singh Chauhan, Costin Anghel, François Krummenacher, Renaud Gillon, Andre Baguenier, Bart Desoete, Steven Frere, Adrian Mihai Ionescu, Michel Declercq
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor. ISQED (2006)