Pin Su

Publication Activity (10 Years)

Years Active: 2000-2017
Publications (10 Years): 9

Top Topics

Directional Information

Fluorescence Microscopy Images

Top Venues

Microelectron. Reliab.

Publications

Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. ISCAS (2017)
Jian-Hao Wang, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling. ICICDT (2016)
Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. ISCAS (2016)
Chang-Hung Yu, Pin Su, Ching-Te Chuang
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells. ISLPED (2016)
Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. ISCAS (2015)
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. ICICDT (2015)
Ko-Chun Lee, Ming-Long Fan, Pin Su
Investigation and comparison of analog figures-of-merit for TFET and FinFET considering work-function variation. Microelectron. Reliab. 55 (2) (2015)
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. SoCC (2015)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. ISCAS (2015)
Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. Microelectron. Reliab. 54 (4) (2014)
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. ISCAS (2014)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (4) (2014)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. ISCAS (2014)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. ISLPED (2014)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. ISQED (2013)
Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. ICICDT (2013)
Ming-Fu Tsai, Jen-Huan Tsai, Ming-Long Fan, Pin Su, Ching-Te Chuang
Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM. APCCAS (2012)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. ESSDERC (2012)
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. APCCAS (2012)
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. ESSDERC (2012)
Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 20 (7) (2012)
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. ICICDT (2012)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Analysis of power-performance for ultra-thin-body GeOI logic circuits. ISLPED (2011)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (3) (2011)
Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ISLPED (2009)
Pin Su, Samel K. H. Fung, Peter W. Wyatt, Hui Wan, Mansun Chan, Ali M. Niknejad, Chenming Hu
A unified model for partial-depletion and full-depletion SOI circuit designs: using BSIMPD as a foundation. CICC (2003)
Pin Su, Samel K. H. Fung, Weidong Liu, Chenming Hu
Studying the Impact of Gate Tunneling on Dynamic Behaviors of Partially-Depleted SOI CMOS Using BSIMPD. ISQED (2002)
Hajime Nakayama, Pin Su, Chenming Hu, Motoaki Nakamura, Hiroshi Komatsu, Kaneyoshi Takeshita, Yasutoshi Komatsu
Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS. CICC (2001)
Pin Su, Samuel K. H. Fung, Stephen Tang, Fariborz Assaderaghi, Chenming Hu
BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. CICC (2000)