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Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits.
Shao-Yu Yang
Yin-Nien Chen
Ming-Long Fan
Vita Pi-Ho Hu
Pin Su
Ching-Te Chuang
Published in:
ICICDT (2013)
Keyphrases
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logic circuits
low power
power consumption
functional decomposition
real time
case study
heuristic search
data transmission
logic synthesis