Ching-Te Chuang

Publication Activity (10 Years)

Years Active: 1996-2019
Publications (10 Years): 14

Top Venues

ISCAS

SoCC

IEEE Trans. Circuits Syst. I Regul. Pap.

VLSI-DAT

Publications

Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. SoCC (2019)
Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. VLSI-DAT (2018)
Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. SoCC (2018)
Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS (2017)
Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. 11 (5) (2017)
Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang
Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. ISCAS (2017)
Jian-Hao Wang, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling. ICICDT (2016)
Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. SoCC (2016)
Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. ISCAS (2016)
Shang-Lin Wu, Chien-Yu Lu, Ming-Hsien Tu, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line. Microelectron. J. 51 (2016)
Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. ISCAS (2016)
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS (2016)
Chang-Hung Yu, Pin Su, Ching-Te Chuang
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells. ISLPED (2016)
Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT (2015)
Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. ISCAS (2015)
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. ICICDT (2015)
Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang
Energy-efficient gas recognition system with event-driven power control. SoCC (2015)
Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. VLSI-DAT (2015)
Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. SoCC (2015)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. ISCAS (2015)
Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. Microelectron. Reliab. 54 (4) (2014)
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. ISCAS (2014)
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. 8 (6) (2014)
Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (4) (2014)
Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. A-SSCC (2014)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. ISCAS (2014)
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. SoCC (2014)
Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC (2014)
Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS (2014)
Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, Ho-Ming Tong
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC (2014)
Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, Wei Hwang
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. IEEE Trans. Circuits Syst. II Express Briefs (3) (2014)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. ISLPED (2014)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT (2014)
Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen
Low temperature (<180 °C) bonding for 3D integration. 3DIC (2013)
Nan-Chun Lien, Ching-Te Chuang, Wen-Rong Wu
Method for resolving simultaneous same-row access in Dual-Port 8T SRAM with asynchronous dual-clock operation. SoCC (2013)
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. ISLPED (2013)
Chien-Yu Lu, Ching-Te Chuang
A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance. SoCC (2013)
Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS (2013)
Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC (2013)
Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. IEEE Trans. Very Large Scale Integr. Syst. 21 (9) (2013)
Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS (2013)
Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. ISCAS (2013)
Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC (2013)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. ISQED (2013)
Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. ICICDT (2013)
Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT (2012)
Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
Testing strategies for a 9T sub-threshold SRAM. ITC (2012)
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. ISCAS (2012)
Ming-Fu Tsai, Jen-Huan Tsai, Ming-Long Fan, Pin Su, Ching-Te Chuang
Variation tolerant CLSAs for nanoscale Bulk-CMOS and FinFET SRAM. APCCAS (2012)
Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. SoCC (2012)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. ESSDERC (2012)
Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS (2012)
Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS (2012)
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. APCCAS (2012)
Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. ESSDERC (2012)
Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 20 (7) (2012)
Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED (2012)
Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC (2012)
Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT (2012)
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. IEEE J. Solid State Circuits 47 (6) (2012)
Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. ICICDT (2012)
Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC (2011)
Hao-I Yang, Wei Hwang, Ching-Te Chuang
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
8T single-ended sub-threshold SRAM with cross-point data-aware write operation. ISLPED (2011)
Hao-I Yang, Wei Hwang, Ching-Te Chuang
Impacts of gate-oxide breakdown on power-gated SRAM. Microelectron. J. 42 (1) (2011)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Analysis of power-performance for ultra-thin-body GeOI logic circuits. ISLPED (2011)
Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (3) (2011)
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2010)
Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. Very Large Scale Integr. Syst. 18 (1) (2010)
Ching-Te Chuang
Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits. ISCAS (2009)
Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Yue Tan
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. IEEE J. Solid State Circuits 44 (3) (2009)
Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
Asymmetrical Write-assist for single-ended SRAM operation. SoCC (2009)
Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. 49 (6) (2009)
Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das
Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD (2009)
Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang
Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ISLPED (2009)
Hao-I Yang, Ching-Te Chuang, Wei Hwang
Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. ISCAS (2009)
Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang
A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. ISCAS (2009)
Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown
On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ISQED (2008)
Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, Fadi H. Gebara, Kevin J. Nowka
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. IEEE Trans. Very Large Scale Integr. Syst. 16 (12) (2008)
Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process. IEEE J. Solid State Circuits 43 (9) (2008)
Koushik K. Das, Ching-Te Chuang, Richard B. Brown
Reducing parasitic BJT effects in partially depleted SOI digital logic circuits. Microelectron. J. 39 (2) (2008)
Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED (2008)
Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design (2008)
Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS (2008)
Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS (2008)
Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design (2008)
Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ICCD (2008)
Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. ISLPED (2007)
Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED (2007)
Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design (2007)
Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure. ISSCC (2007)

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Ching-Te Chuang