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A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist.

Yi-Wei ChiuYu-Hao HuMing-Hsien TuJun-Kai ZhaoShyh-Jye JouChing-Te Chuang
Published in: ISLPED (2013)
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