Shyh-Jye Jou

ORCID

Publication Activity (10 Years)

Years Active: 1994-2023
Publications (10 Years): 56

Top Venues

ISCAS

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

VLSI-DAT

Publications

Henry Lopez Davila, Tsung-Han Wu, Shyh-Jye Jou, Sau-Gee Chen, Pei-Yun Tsai
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications. IEEE Trans. Very Large Scale Integr. Syst. 31 (1) (2023)
Chih-Wei Jen, Hung-Chih Liu, Zheng-Chun Huang, Nai-Cheng Xue, Shyh-Jye Jou
A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers. IEEE J. Emerg. Sel. Topics Circuits Syst. 13 (2) (2023)
Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC (2023)
Chung-Lun Tu, Chin-Ming Chang, Shyh-Jye Jou
Offline and Time-variant EVD-based Closed-loop Digital Predistortion Design for Sub-THz Power Amplifier Array in Basedband Transmitter. ISCAS (2023)
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
Hardware-Robust In-RRAM-Computing for Object Detection. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Shen-Zhe Lu, Nai-Cheng Xue, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou
Low-Complexity Pseudo Direct Learning Digital Pre-Distortion Architecture for Nonlinearity and Memory Effect of Power Amplifier in mmWave Baseband Transmitter. ISCAS (2022)
Kang-Lun Chiu, Hsun-Wei Chan, Hsuan-Ping Chiu, Chun-Yi Liu, Chih-Wei Jen, Shyh-Jye Jou
Design of a mmWave Digital Baseband Receiver Integrated with WOLA-CP-OFDM Technique. ISCAS (2022)
Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. DATE (2022)
Chung-Lun Tu, Tse-Yuan Lin, Kang-Lun Chiu, Shyh-Jye Jou, Pei-Yun Tsai
Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System. ISCAS (2022)
Chi Liu, Shao-Tzu Li, Tong-Lin Pan, Cheng-En Ni, Yun Sung, Chia-Lin Hu, Kang-Yu Chang, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. VLSI-DAT (2022)
Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou
A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization. CoRR (2022)
Yu-Hsiang Chiang, Cheng-En Ni, Yun Sung, Tuo-Hung Hou, Tian-Sheuan Chang, Shyh-Jye Jou
Hardware-Robust In-RRAM-Computing for Object Detection. CoRR (2022)
Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen
On Optimizing Capacitor Array Design for Advanced Node SAR ADC. SMACD (2022)
Yu-Hsiang Chiang, Tian-Sheuan Chang, Shyh-Jye Jou
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization. IEEE Trans. Very Large Scale Integr. Syst. 30 (9) (2022)
Hung-Chih Liu, Zheng-Chun Huang, Ngoc-Giang Doan, Chih-Wei Jen, Shyh-Jye Jou
Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (2) (2022)
Hsun-Wei Chan, Wei-Che Lee, Kang-Lun Chiu, Chih-Wei Jen, Shyh-Jye Jou
A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems. IEEE Trans. Very Large Scale Integr. Syst. 29 (5) (2021)
Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. ISCAS (2021)
Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
On Reconfiguring Memory-Centric AI Edge Devices for CIM. ISOCC (2021)
Yu-Hsien Lin, Chi Liu, Chia-Lin Hu, Kang-Yu Chang, Jia-Yin Chen, Shyh-Jye Jou
A Reconfigurable In-SRAM Computing Architecture for DCNN Applications. VLSI-DAT (2021)
Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. ICCAD (2020)
Ngoc-Giang Doan, Hung-Chih Liu, Chih-Wei Jen, Shyh-Jye Jou
Digital Self-Healing using Smart Sensing Technique for IQ Mismatch and LO Leakage against Non-Flat Path Response in mmWave Communication System. ISCAS (2020)
Henry Lopez Davila, Hsun-Wei Chan, Kang-Lun Chiu, Pei-Yun Tsai, Shyh-Jye Jou
and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Hung-Chih Liu, Hsun-Wei Chan, Henry Lopez Davila, Kang-Lun Chiu, Chih-Wei Jen, Ngoc-Giang Doan, Zheng-Chun Huang, Hsin-Ting Chang, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou
A 16/64 QAM Baseband SoC for mm-Wave Transceiver with Self-Healing for FD/FI IQ Mismatch, LO Leakage and CFO/SCO/PNC. A-SSCC (2020)
Kang-Lun Chiu, Pai-Hsiang Shen, Bing-Ru Lin, Wei-Han Hsiao, Shyh-Jye Jou, Chia-Chi Huang
Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Chee-Kit Ng, Yu-Chun Lin, Shyh-Jye Jou
A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems. VLSI-DAT (2019)
Chee-Kit Ng, Kang-Lun Chiu, Yu-Chun Lin, Shyh-Jye Jou
A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems. ISCAS (2019)
C. Y. He, K. H. Tang, T. S. Chen, K. Y. Chang, C. H. Lin, K. Sato, Shyh-Jye Jou, P. H. Chen, H. M. Chen, B. D. Rong, K. Itoh
Sub-ns Access Sub-mW/GHz 32 Kb SRAM with 0.45 V Cross-Point-5T Cell and Built-in Y_ Line. A-SSCC (2019)
Kang-Lun Chiu, Hsun-Wei Chan, Wei-Che Lee, Chang-Ting Wu, Henry Lopez Davila, Hung-Chih Liu, Meng-Yuan Huang, Chun-Yi Liu, Tsai-Hua Lee, Hsin-Ting Chang, Chih-Wei Jen, Nien-Hsiang Chang, Pei-Yun Tsai, Yen-Cheng Kuan, Shyh-Jye Jou
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications. A-SSCC (2019)
Yu-Cheng Su, Kang-Yu Chang, Yu-Tung Chin, Chia-Wen Chang, Shyh-Jye Jou
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays. ASICON (2019)
Chih-Wei Jen, Hung-Wei Yang, Hsun-Wei Chan, Hung-Chih Liu, Henry Lopez Davila, Chun-Yi Liu, Shyh-Jye Jou
Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band. ISCAS (2018)
Chee-Kit Ng, Yu-Chun Lin, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou
A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems. ISCAS (2018)
Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Chih-Wei Jen, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2017)
Chun-Yi Liu, Edmund Wen Jen Leong, Chang-Ting Wu, Meng-Siou Sie, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou
A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band. IEEE J. Emerg. Sel. Topics Circuits Syst. 7 (4) (2017)
Chun-Yi Liu, Yu-Cheng Yao, Meng-Siou Sie, Edmund Wen Jen Leong, Henry Lopez Davila, Chih-Wei Jen, Shyh-Jye Jou
Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band. ISCAS (2017)
Hsun-Wei Chan, Chang-Ting Wu, Chih-Wei Jen, Chun-Yi Liu, Wei-Che Lee, Shyh-Jye Jou
A pseudo MMSE linear equalizer for 60GHz single carrier baseband receiver. ASICON (2017)
Wei-Chang Liu, Ching-Da Chan, Shuo-An Huang, Chi-Wei Lo, Chia-Hsiang Yang, Shyh-Jye Jou
Error-resilient sequential cells with successive time borrowing for stochastic computing. ICASSP (2016)
Chia-Wen Chang, Kai-Yu Lo, Hossameldin A. Ibrahim, Ming-Chiuan Su, Yuan-Hua Chu, Shyh-Jye Jou
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. IEICE Trans. Electron. (4) (2016)
Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou
Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series. Circuits Syst. Signal Process. 35 (8) (2016)
Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. ISCAS (2016)
Chih-Feng Wu, Wei-Chang Liu, Chia-Chun Tsui, Chun-Yi Liu, Meng-Siou Sie, Shyh-Jye Jou
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Chih-Wei Jen, Shyh-Jye Jou
A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver. ISCAS (2016)
Chun-Yi Liu, Meng-Siou Sie, Edmund Wen Jen Leong, Yu-Cheng Yao, Henry Lopez Davila, Chih-Wei Jen, Wei-Chang Liu, Shyh-Jye Jou
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2016)
Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems. IEEE ACM Trans. Audio Speech Lang. Process. 24 (8) (2016)
Hung-Wei Yang, Yongyu He, Chih-Wei Jen, Chun-Yi Liu, Shyh-Jye Jou, Xuefeng Yin, Meng Ma, Bingli Jiao
Interference measurement and analysis of full-duplex wireless system in 60 GHz band. APCCAS (2016)
Pranav Arya, Liang-Yu Huang, Wei-Chang Liu, Hsin-Ting Chang, Chih-Wei Jen, Chih-Feng Wu, Shyh-Jye Jou
Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system. ICCE-TW (2015)
Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou
A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Liang-Yu Huang, Chia-Yi Wu, Chun-Yi Liu, Wei-Chang Liu, Chih-Feng Wu, Shyh-Jye Jou
A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems. VLSI-DAT (2015)
Wen-Quan He, Yu-Chun Lin, Jui-Yi Hung, Shyh-Jye Jou
Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead. ASICON (2015)
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. ISCAS (2015)
Chia-Wen Chang, Yuan-Hua Chu, Shyh-Jye Jou
A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications. IEICE Trans. Electron. (8) (2015)
Henry Lopez Davila, Chun-Yi Liu, Wei-Chang Liu, Shen-Jui Huang, Shyh-Jye Jou, Sau-Gee Chen
A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems. SoCC (2015)
Chien-Yu Lu, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Ya-Ping Wu, Chung-Ping Huang, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Nicholas Preyss, Christian Senning, Andreas Burg, Wei-Chang Liu, Chun-Yi Liu, Shyh-Jye Jou
A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm. A-SSCC (2015)
Wen-Quan He, Yuan-Ho Chen, Shyh-Jye Jou
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Wei-Chang Liu, Ting-Chen Wei, Ya-Shiue Huang, Ching-Da Chan, Shyh-Jye Jou
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2015)
Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Wei-Chang Liu, Fu-Chun Yeh, Chia-Yi Wu, Ting-Chen Wei, Ya-Shiue Huang, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen
An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band. ISCAS (2014)
Cheng-Wen Wei, Cheng-Chun Tsai, FanJiang Yi, Tian-Sheuan Chang, Shyh-Jye Jou
Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application. IET Circuits Devices Syst. 8 (6) (2014)
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang
Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing. IEEE ACM Trans. Audio Speech Lang. Process. 22 (8) (2014)
Yi FanChiang, Cheng-Wen Wei, Yi-Le Meng, Yu-Wen Lin, Shyh-Jye Jou, Tian-Sheuan Chang
Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing". IEEE ACM Trans. Audio Speech Lang. Process. 22 (12) (2014)
Cheng-Yen Yang, Chih-Wei Liu, Shyh-Jye Jou
An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids. ICASSP (2014)
Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. SoCC (2014)
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. SoCC (2014)
Sau-Gee Chen, Shen-Jui Huang, Mario Garrido, Shyh-Jye Jou
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2014)
Yu-Jui Chen, Cheng-Wen Wei, Yi FanChiang, Yi-Le Meng, Yi-Cheng Huang, Shyh-Jye Jou
Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2014)
Chih-Wei Jen, Shyh-Jye Jou
Blind ICA detection based on second-order cone programming for MC-CDMA systems. EURASIP J. Adv. Signal Process. 2014 (2014)
Kuo-Chiang Chang, Shien-Chun Luo, Ching-Ji Huang, Chih-Wei Liu, Yuan-Hua Chu, Shyh-Jye Jou
An ultra-low voltage hearing aid chip using variable-latency design technique. ISCAS (2014)
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. ISLPED (2013)
Ching-Da Chan, Wei-Chang Liu, Chia-Hsiang Yang, Shyh-Jye Jou
Power and area reduction in multi-stage addition using operand segmentation. VLSI-DAT (2013)
Yi-Cheng Huang, Fan-Chiang Yi, Shyh-Jye Jou
A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids. SiPS (2013)
Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS (2013)
Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou
A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. CICC (2013)
Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ya-Shiue Huang, Tai-Yang Liu, Shen-Jui Huang, Ching-Da Chan, Shyh-Jye Jou, Sau-Gee Chen
A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c. ISCAS (2013)
Li-Rong Wang, Kai-Yu Lo, Shyh-Jye Jou
A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design. IEICE Trans. Electron. (10) (2013)
Hsiao-Yun Chen, Wei-Kai Chang, Shyh-Jye Jou
A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2013)
Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC (2013)
Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou
STBC-OFDM Downlink Baseband Receiver for Mobile WMAN. IEEE Trans. Very Large Scale Integr. Syst. 21 (1) (2013)
Wei-Chang Liu, Fu-Chun Yeh, Ting-Chen Wei, Ching-Da Chan, Shyh-Jye Jou
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2013)
Cheng-Yen Yang, Wen-Sheng Chou, Kuo-Chiang Chang, Chih-Wei Liu, Tai-Shih Chi, Shyh-Jye Jou
Spatial-cue-based multi-band binaural noise reduction for hearing aids. SiPS (2013)
Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT (2012)
Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
Testing strategies for a 9T sub-threshold SRAM. ITC (2012)
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. ISCAS (2012)
Jhih-Cing Sun, Jou-Ling Chen, Yi-Hung Shen, Shiu-Chain You, Shyh-Jye Jou, Tzu-Hsien Sang
A 80-uW 2-Mb/s transceiver for human body channel binaural communication. BioCAS (2012)
Yu-Chun Lin, Shyh-Jye Jou, Muh-Tian Shiue
High throughput concurrent lookahead adaptive decision feedback equaliser. IET Circuits Devices Syst. 6 (1) (2012)
Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS (2012)
Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS (2012)
Jou-Ling Chen, Jhih-Cing Sun, Yi-Hung Shen, Tzu-Hsien Sang, Tian-Sheuan Chang, Shyh-Jye Jou
A low-power body-channel communication system for binaural hearing aids. BioCAS (2012)
Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Michel Brillouët, Shyh-Jye Jou, C. Patrick Yue
Welcome from the general chairs. VLSI-DAT (2012)
Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT (2012)
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. IEEE J. Solid State Circuits 47 (6) (2012)
Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou
Sub µW Noise Reduction for CIC Hearing Aids. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 47 (9) (2012)
Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC (2011)
Li-Rong Wang, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design. IEICE Trans. Electron. (6) (2011)
Ming-Chiuan Su, Shyh-Jye Jou
Digitally-controlled cell-based oscillator with multi-phase differential outputs. ASICON (2011)
Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
8T single-ended sub-threshold SRAM with cross-point data-aware write operation. ISLPED (2011)
Chia-Wen Chang, Shyh-Jye Jou, Yuan-Hua Chu
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. ASICON (2011)

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Shyh-Jye Jou