A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.
Chi-Hao HongYi-Wei ChiuJun-Kai ZhaoShyh-Jye JouWen-Tai WangReed LeePublished in: SoCC (2014)
Keyphrases
- cmos technology
- low power
- low voltage
- high power
- power consumption
- high speed
- low cost
- random access memory
- wide dynamic range
- leakage current
- mixed signal
- single chip
- silicon on insulator
- image sensor
- digital signal processing
- power management
- low power consumption
- power dissipation
- energy saving
- machine vision
- image enhancement
- nm technology
- real time