Yi-Wei Chiu

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 2

Top Topics

Cmos Technology

Data Processing

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yen-Wen Chen, Yi-Wei Chiu, Yu-Sin Liu, Chih-Yu Huang, Yu-Chun Shen
AI Powered Multi-model Content Creation For Virtual Gallery Using Learning Machine. UEMCON (2023)
Yi-Wei Chiu, Yu-Hao Hu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. ISCAS (2016)
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee
A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. ISCAS (2015)
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Yuan-Hua Chu, Shyh-Jye Jou, Ching-Te Chuang
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. SoCC (2014)
Yi-Wei Chiu, Yu-Hao Hu, Ming-Hsien Tu, Jun-Kai Zhao, Shyh-Jye Jou, Ching-Te Chuang
A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. ISLPED (2013)
Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS (2012)
Yi-Wei Chiu, Jihi-Yu Lin, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
8T single-ended sub-threshold SRAM with cross-point data-aware write operation. ISLPED (2011)
Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee
A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. ISCAS (2008)