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A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive.
Chi-Hao Hong
Yi-Wei Chiu
Jun-Kai Zhao
Shyh-Jye Jou
Wen-Tai Wang
Reed Lee
Published in:
ISCAS (2015)
Keyphrases
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high speed
low power
random access memory
power consumption
cmos technology
nm technology
knowledge base
shift register
data transmission
high speed networks
power reduction
real time
data acquisition
line segments
frame rate
design considerations