Ming-Chien Tsai

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

Metal Oxide Semiconductor

Design Considerations

Analog To Digital Converter

Top Venues

IEEE J. Solid State Circuits

Publications

Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT (2012)
Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. ISCAS (2012)
Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS (2012)
Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT (2012)
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. IEEE J. Solid State Circuits 47 (6) (2012)
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2010)
Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
Asymmetrical Write-assist for single-ended SRAM operation. SoCC (2009)
Ming-Chien Tsai, Ching-Hwa Cheng
A full-synthesizable high-precision built-in delay time measurement circuit. ASP-DAC (2009)
Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang
An All-Digital High-Precision Built-In Delay Time Measurement Circuit. VTS (2008)
Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai
High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability. APCCAS (2006)