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An all-digital bit transistor characterization scheme for CMOS 6T SRAM array.
Geng-Cing Lin
Shao-Cheng Wang
Yi-Wei Lin
Ming-Chien Tsai
Ching-Te Chuang
Shyh-Jye Jou
Nan-Chun Lien
Wei-Chiang Shih
Kuen-Di Lee
Jyun-Kai Chu
Published in:
ISCAS (2012)
Keyphrases
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random access memory
design considerations
low power
analog to digital converter
low voltage
circuit design
power consumption
high speed
metal oxide semiconductor
mixed signal
protection scheme
leakage current
low cost
neural network
digital content
flash memory
memory access
infrared