Wei Hwang

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 17

Top Venues

SoCC

ISCAS

VLSI-DAT

CICC

Publications

Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. ISOCC (2022)
Po-Tsang Huang, I-Chen Wu, Chin-Yang Lo, Wei Hwang
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. IEEE Open J. Circuits Syst. 2 (2021)
Po-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. ISOCC (2021)
Wei Lu, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (4) (2021)
Chin-Yang Lo, Po-Tsang Huang, Wei Hwang
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. AICAS (2020)
Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. SoCC (2020)
I-Chen Wu, Po-Tsang Huang, Chin-Yang Lo, Wei Hwang
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. AICAS (2019)
Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. SoCC (2019)
Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. VLSI-DAT (2018)
Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. SoCC (2018)
Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS (2017)
Yu-Hsuan Lin, Shih-Fan Peng, Wei Hwang
Wide-I/O 3D-staked DRAM controller for near-data processing system. VLSI-DAT (2017)
Chung-Shiang Wu, Hui-Hsuan Lee, Po-Hung Chen, Wei Hwang
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. 11 (5) (2017)
Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. SoCC (2016)
Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS (2016)
Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT (2015)
Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang
An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. ISCAS (2015)
Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang
Energy-efficient gas recognition system with event-driven power control. SoCC (2015)
Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC (2015)
Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. VLSI-DAT (2015)
Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. 8 (6) (2014)
Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. A-SSCC (2014)
Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. SoCC (2014)
Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC (2014)
Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS (2014)
Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang
A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC (2014)
Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang
A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC (2014)
Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, Ho-Ming Tong
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC (2014)
Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, Wei Hwang
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. IEEE Trans. Circuits Syst. II Express Briefs (3) (2014)
Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT (2014)
Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen
Low temperature (<180 °C) bonding for 3D integration. 3DIC (2013)
Dao-Ping Wang, Hon-Jarn Lin, Wei Hwang
A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation. J. Low Power Electron. 9 (1) (2013)
Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS (2013)
Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC (2013)
Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang
A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. SoCC (2013)
Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS (2013)
Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. ISCAS (2013)
Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC (2013)
Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT (2012)
Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang
An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. SoCC (2012)
Wei-Chih Hsieh, Wei Hwang
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Dao-Ping Wang, Wei Hwang
A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation. J. Low Power Electron. 8 (4) (2012)
Po-Tsang Huang, Wei Hwang
Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electr. Comput. Eng. 2012 (2012)
Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. SoCC (2012)
Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS (2012)
Ming-Hung Chang, Yi-Te Chiu, Wei Hwang
Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (7) (2012)
Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED (2012)
Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC (2012)
Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT (2012)
Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang
Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS. J. Low Power Electron. 8 (1) (2012)
Po-Jen Yang, Po-Tsang Huang, Wei Hwang
Substrate noise suppression technique for power integrity of TSV 3D integration. ISCAS (2012)
Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang
A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. VLSI-DAT (2012)
Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Po-Tsang Huang, Yung Chang, Wei Hwang
On-demand memory sub-system for multi-core SoCs. SoCC (2011)
Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC (2011)
Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang
A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. ISLPED (2011)
Hao-I Yang, Wei Hwang, Ching-Te Chuang
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Hao-I Yang, Wei Hwang, Ching-Te Chuang
Impacts of gate-oxide breakdown on power-gated SRAM. Microelectron. J. 42 (1) (2011)
Po-Tsang Huang, Wei Hwang
Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2011)
Wei-Chih Hsieh, Wei Hwang
Adaptive Power Control Technique on Power-Gated Circuitries. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Po-Tsang Huang, Wei Hwang
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. IEEE J. Solid State Circuits 46 (2) (2011)
Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang
Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. ISLPED (2011)
Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang
An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. SoCC (2011)
Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6 (4) (2010)
Wei-Chih Hsieh, Wei Hwang
Low quiescent current variable output digital controlled voltage regulator. ISCAS (2010)
Ming-Hung Chang, Jung-Yi Wu, Wei-Chih Hsieh, Shang-Yuan Lin, You-Wei Liang, Wei Hwang
High efficiency power management system for solar energy harvesting applications. APCCAS (2010)
Tien-Hung Lin, Po-Tsang Huang, Wei Hwang
Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC (2010)
Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, Wei Hwang
Fully on-chip temperature, process, and voltage sensors. ISCAS (2010)
Yi-Ming Chang, Ming-Hung Chang, Wei Hwang
A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. SoCC (2009)
Po-Tsang Huang, Wei Hwang
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC (2009)
Hao-I Yang, Ching-Te Chuang, Wei Hwang
Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. ISCAS (2009)
Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang
"Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS (2008)
Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS (2008)
Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. SoCC (2008)
Wei-Chih Hsieh, Wei Hwang
In-situ self-aware adaptive power control system with multi-mode power gating network. SoCC (2008)
Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS (2008)
Mu-Tien Chang, Wei Hwang
A fully-differential subthreshold SRAM cell with auto-compensation. APCCAS (2008)
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC (2008)
Hao-I Yang, Ssu-Yun Lai, Wei Hwang
Low-power floating bitline 8-T SRAM design with write assistant circuits. SoCC (2008)
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC (2007)
Chang-Hsuan Chang, Ming-Hung Chang, Wei Hwang
A flexible two-layer external memory management for H.264/AVC decoder. SoCC (2007)
Ming-Hung Chang, Zong-Xi Yang, Wei Hwang
A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. ISCAS (2007)
Wei-Chih Hsieh, Wei Hwang
Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. ISCAS (2007)
Po-Tsang Huang, Wei-Keng Chang, Wei Hwang
Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS (2006)
Jen-Wei Yang, Po-Tsang Huang, Wei Hwang
On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS (2006)
Po-Tsang Huang, Wei Hwang
2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS (2006)
Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang
A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. ISCAS (2006)
Chi-Chen Lai, Wei Hwang
A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. APCCAS (2006)
Tzu-Chiang Chao, Wei Hwang
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. ISCAS (2006)
Chung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang
Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM. MTDT (2005)
Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ISCAS (1) (2005)
Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. J. VLSI Signal Process. 38 (2) (2004)
Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. 47 (2-3) (2003)
Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang
Multiplier architecture power consumption characterization for low-power DSP applications. ICECS (2002)
Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI (2001)
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
Design Of Provably Correct Storage Arrays. VLSI Design (2001)

Wei Hwang.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Wei Hwang