A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation.
Dao-Ping WangWei HwangPublished in: J. Low Power Electron. (2012)
Keyphrases
- low power
- power consumption
- cmos technology
- nm technology
- low cost
- high speed
- power reduction
- high power
- single chip
- wireless transmission
- digital signal processing
- gate array
- low power consumption
- vlsi architecture
- image sensor
- logic circuits
- power saving
- random access memory
- vlsi circuits
- signal processor
- container terminal
- low voltage