A 1.7mW all digital phase-locked loop with new gain generator and low power DCO.
Tzu-Chiang ChaoWei HwangPublished in: ISCAS (2006)
Keyphrases
- low power
- power consumption
- phase locked loop
- mixed signal
- low cost
- high speed
- high voltage
- multipath
- single chip
- low power consumption
- high power
- digital signal processing
- wireless transmission
- logic circuits
- power dissipation
- vlsi architecture
- vlsi circuits
- cmos technology
- power reduction
- image sensor
- gate array
- delay insensitive
- cmos image sensor