A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS.

Ming-Hung Chang Yi-Te Chiu Shu-Lin Lai Wei Hwang

Published in: ISLPED (2011)

Keyphrases

random access memory
low voltage
power consumption
cmos technology
low power
nm technology
leakage current
design considerations
flip flops
embedded dram
protection scheme
low cost
knowledge base
power dissipation
bit string
focal plane
mixed signal
pseudorandom
parallel processing
successive approximation
high speed